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Use ATA Interfaces For General-Purpose I/O Applications

Using modern PC interfaces for connecting application-specific hardware can create a wide range of problems for embedded designers （e.g.， slow communication and long latencies）.In this article， Wolfgang describes a viable alternative： an ATA interface. Employing ATA as the low-latency embedded interface allows you to apply miniaturized motherboards instead of typical industrial platforms， which are considerably more expensive.

When PC systems are used in embedded systems， it is necessary to select appropriate interfaces for attaching application-specific hardware. The basic requirements are obvious. Hardware as well as software should be easy to develop and inexpensive. Low latencies are more important than impressive data rates.

The legacy interfaces of the past were comparatively well suited to these requirements. To build an adapter for the ISA bus or the parallel port requires only a few LS TTL packages. Attachment via RS-232 requires only a small microcontroller and a receiver/transmitter combo IC （like the good old MAX232）.

But many contemporary PCs have no legacy interface at all. PC hardware in "industrial" form factors（like PC/104 or PICMG） supports those interfaces， but it is expensive.

Modern PC interfaces are designed mainly with multimedia and gaming applications and with ease of use in mind （e.g.， extreme data rates， support of continuous datastreams， and dynamic attach/detach）。 Exploiting these interfaces for connecting applicationspecific hardware poses some problems. Latencies can be long. This relates especially to USB and Ethernet. Typical latencies are in the order of 10 to 20 ms regardless of the data rate. Readily available bread-and-butter solutions （above all， the serial communication over USB） are comparatively slow. Developing full-blown high-performance solutions （based on USB，Firewire， PCI Express， and the like）

requires a lot of effort. More often than not， applying contemporary interface standards will lead to spending more money. Various fees have to be paid for licenses， for membership in the standardization committee， for acquiring a vendor ID， for getting the design certified （to ensure conformity），and more.

EXPLOITING THE ATA INTERFACE
One legacy interface boasting low latencies and high data rates can be found on even the most contemporary motherboards-the advanced technology attachment （ATA） interface. ATA is still a mainstream drive interface，so long-term availability could be taken for granted. The most compelling advantage is simplicity. The legacy ATA interface （Parallel ATA） is essentially a modified ISA bus. Hence， it should be easy to develop I/O adapter hardware. The hardware/ software API is straightforward-a small register file accessible by I/O instructions. ATA registers can be accessed directly （under DOS or Linux） or via comparatively simple port drivers. Serial ATA （SATA） is principally nothing more than two wire pairs to push around register contents between the host adapter and the attached device. Because ATA is essential for booting the system，appropriate support is deeply embedded within the BIOS and the operating systems.

In this article， I will concentrate on programmed I/O （PIO） operation of the parallel ATA （PATA） interface without provisions for supporting attachment of SATA protocol converters （see Figure 1）.PATA is still supported on new motherboards in small form factors （such as Mini-ITX or Nano-ITX）， particularly because it is still a mainstream interface for optical drives. Employing ATA as the low-latency embedded interface enables you to apply such motherboards instead of typical industrial platforms（like PC/104， EBX， EPIC， or PICMG），which are considerably more expensive（see Photo 1）.

Typical ATA I/O adapters will fit into small CPLDs. Eventually， the application-specific circuitry could find its place within the same CPLD，too （see Figure 2a）。 ATA interface adapters can be provided for the attachment of widely available I/O hardware， like Opto 22-compatible racks， ISA or PCI I/O cards， and PC/104 modules （see Figure 2b）.

MOTIVATION
Low-latency control problems could be solved outside of the PC by providing the appropriate hardware. A microcontroller connected via a serial port，USB， or Ethernet is an obvious example. On the market， such hardware（integrated circuits， modules， starter kits， and so on） is available in abundance. Contemporary development software is comfortable and， more often than not， free.

But this approach has severe drawbacks too. Generally， there is the problem of functional partitioning between software and external hardware，as well as between two programs：one running on the PC and one on the microcontroller. It poses some challenges.

In embedded systems design， typical application problems lead to some kind of state machine， executing the following steps： first， fetch input data（from sensors， operator panels， and the like）； second， perform the necessary decisions and calculations to determine the next state and the outputs；third， emit output data （to actuators，displays， and the like）； and finally，return to the first step.

Functional partitioning is an art rather than an exact science. It has to be done even if you can get the microcontroller together with its programming environment for free. Whether it is a trivial task or not depends on the complexity of the second step. If the decisions and calculations to be executed in this step require a lot of computing power and memory capacity， low-cost external hardware （i.e.， PIC， AVR， or a small FPGA） will not do. In some cases，intermediate microcontrollers （i.e.，Blackfin or ARM） would help. But many applications have to cope with vast performance requirements and high complexity. Many users expect the look and feel of Windows and the availability of advanced graphics， database and networking services，and so on. This way， comparatively humble embedded control tasks and typical performance-hungry Windows applications become closely intertwined. Often， a practically viable function partitioning cannot avoid employing external high-performance platforms （e.g.， based on PowerPC or Coldfire processors） running their own real-time OS. （In other words，all of the decisive functions have been delegated to the external subsystem. The Windows PC is merely used as an operating console， file server， print server， and network hub.）

Partitioning splits the development process into independent tasks （i.e.，PC programming， microcontroller programming， and FPGA design）.Without partitioning （all application programs reside in the PC）， program development can be done completely within one environment （like Visual Basic， C#， or Delphi）。 From an average Visual Basic， C#， or Delphi programmer，you can expect a PC-only solution，not a mixture of PC programming，microcontroller programming，and hardware design.

Therefore， many embedded systems designers resort to the alternative approach： leave all program activities to the PC and attach the application-specific hardware via low-latency interfaces， especially via PCI cards， PC/104 modules， and more.

ATA I/O can be seen as a viable alternative in application areas that are the traditional domains of the（expensive） small-form-factor industrial PC modules.

PRINCIPLES OF OPERATION
In the beginning， ATA was a stripped-down ISA bus. The signal lines are shown in Figure 3. Refer to Figure 1 for the principal access cycles. Early host adapters comprised only a data bus buffer and some address decoding circuitry. The addressing provisions were reduced to three address lines and two pre-decoded chip selects， supporting the selec tion of nine registers or I/O ports （see Table 1）。 So， it may seem a somewhat trivial task to design appropriate interface adapter circuitry. Such an adapter would resemble an old-fashioned ISA I/O card， consisting essentially of an address decoder and attached input and output registers.

But this obvious approach will not work flawlessly. Because ATA was not developed as a universal I/O interface，but exclusively as an interface for attaching disk drives and other massstorage devices， some potential conflicts are to be taken into consideration：the activities of the BIOS and the operating system， the design of contemporary host adapters， and the coexistence of I/O adapters and drives（especially at the same ATA cable）.

SYSTEM SOFTWARE
During the boot sequence， the system software （BIOS and operating system）tries to detect which host adapters and drives are present. Because disk drives are essential to boot the system， the activities are deeply embedded within the system software-they are not delegated to device drivers （which could be uninstalled，if necessary）。 Hence， it is not possible to circumvent them. Usually，BIOSes try to detect drives by writing 00H （master） and 10H （slave）into the DH register and reading the DH register‘s content back.

HOST ADAPTERS
ATA host adapters reside in the motherboard chipset. Experiments have shown that host adapters on true legacy （remarkably old） motherboards behave like ISA devices. There are no access restrictions. Data can be written into and read from all ATA registers. But you cannot expect contemporary host adapters to behave the same way. You can rely only on compliance to current versions of the ATA standards.

Although additional ATA ports can be provided easily by insertion of appropriate add-in cards， it is advantageous to allow for the coexistence of I/O adapters and drives at the same cable-especially when the cute， small motherboards are used（see Photo 1）.

PRINCIPAL SOLUTION
The solution relies on a few simple provisions and tricks. I will consider only register addresses， which have no side-effects in the hardware （like command initiation） and for which the ATA standard permits read and write accesses at random. The device/head （DH） register will be used for device and port selection （see Figure 4）.This register will be deliberately prevented from being read. A read access to the DH register will deliver "nothing，"which results in reading a constant value FFH. To avoid conflicts when the BIOS tries to detect the ATA configuration，I will not use the value 0H （in the bit positions 3......0 of the DH register） as a valid port address. So， my adapter will be hidden completely from the configuration software and will pass the boot and initialization sequences without being noticed.

ADDRESS SPACE Four
ATA registers are employed（see Table 1） and 15 of the 16 possible values in the bit positions 3......0 of the DH register are valid for port selection. Accordingly， an I/O adapter may comprise up to 15 selectable ports with up to four addressable registers each. In other words， a register address space of 60 （i.e.，15 × 4） bytes will be supported.

By applying the principles of 48-bit addressing （ATA-6 and higher）， an address space of 2，040 bytes （i.e.， 255 ×8） can be supported. All of the ATA registers used （compare Table 1） are included in the 48-bit addressing scheme.
 
DEVICE SELECTION
Whether the adapter will be selected or not depends on DH register bit position 4 （DEVICE） and an input signal MASTER/SLAVE SELECT. This input can be connected to the interface signal cable select （CSEL） or tied to a fixed potential （low or high）。 To select the device， load the DH register with the corresponding value （with 0，if the I/O adapter is configured as the master， or with 1 if it is configured as the slave）。

MORE THAN ONE ADAPTER IC
It should be possible to attach more than one I/O adapter without resorting to the obvious principle of master/slave selection. An application example is an industrial computer system based on a Nano-ITX motherboard featuring one parallel and two serial ATA ports. The parallel ATA port is used to attach one drive （DVD or flash memory）configured as device 0 （master） and some I/O adapter ICs （CPLDs or FPGAs）， which together constitute the device 1 （slave）.To support such configurations，each adapter IC has to be assigned to a different subset of I/O port addresses. Each adapter should write to ATA registers or drive the ATA data bus only if the DH register contains a valid port address.

PATA CIRCUITRY
An ATA I/O adapter consists of gates and flip-flops. The principle of operation is comparatively simple，especially if only PATA is supported（there are no complex state machines and the like）。 Very basic adapters fit into small CPLDs， containing 32 to 36 macro cells. An appropriate example adapter consists of the ATA frontend circuitry （described below） and one microcontroller-like 8-bit-port comprising a data register and a direction register. But even the detailed schematic of this simple circuit would occupy too much space. Hence， I will concentrate on the basic principles.

REFERENCE DESIGNS
Based on Xilinx XC9500 CPLDs， some ATA I/O adapters have been designed and-of course-tested intensively. Photo 2 shows one of the test platforms. Porting to other families of programmable ICs should pose no difficulties. The design documentation，including complete Xilinx ISE projects， detailed schematics， and descriptions is readily available for downloading. The four designs mentioned below fit into Xilinx XC95108 CPLDs. Expect more to come.

The first design is five universal I/O ports. The I/O ports are similar to the typical I/O ports of wellknown microcontroller families （e.g.，Microchip PIC and Atmel AVR）.Under program control， each of the 40 （i.e.， 5 × 8） I/O lines can be used as an input or as an output. Each I/O port comprises a direction control register （DIR） and a data register （DAT）.The DIR bit positions control the direction of the corresponding I/O pins.

If the DIR bit is set to zero， the pin is configured as an input， with the pin driver in a high-impedance state. If the DIR bit is set to one， the pin is configured as an output. The potential（low or high） on the pin corresponds to the bit in the DAT register.

Contrary to the operation of some microcontroller ports （e.g.， Atmel AVR），only the potentials on the pins can be read back. This Spartan solution was chosen to make the design fit into a 108- macrocell CPLD. Therefore， the modification of DIR and DAT register contents has to be done by software （based on register copies held in RAM）。 With respect to internal processing speed and RAM capacity， PCs are obviously superior to little microcontrollers. Consequently，the speed penalty is negligible.

The second design is 8255 emulation. This circuit behaves like an 8255 in mode 0. In addition to the three 8255 I/O ports， two universal ports are provided.

The third design is ISA interface emulation. The purpose of the circuit is to support ISA I/O cards and， above all， PC/104 I/O modules. Hence， the ISA emulation could be restricted to 8-bit I/O cycles and to the support of ISA interrupts.

The fourth design is parallel port emulation. The circuit behaves like an IEEE 1284 standard printer port （SPP）with optional support for the bidirectional（PS/2） mode. In addition to the 17 signal lines of the parallel port， two universal ports are provided.
 
RELATED SOFTWARE
ATA interface adapters should be programmed like microcontrollers‘ I/O ports. The description of a particular interface adapter will show the accessible registers， the corresponding addresses， and if necessary， the meaning or effect of each individual bit position.

The only difference between the low-level programming of a conventional I/O circuit （like the vintage 8255） and corresponding ATA I/O programming is that the I/O register access must be preceded by loading the device selection bit together with the port address into the DH register. Source code examples （in C） are available on the Circuit Cellar FTP site.

ATA I/O & THE OS
Under Linux， DOS， or in stand-alone programs， ATA I/O hardware can be accessed directly by I/O instructions. It could not be simpler （especially when compared to attempts to program a USB host adapter without system-provided APIs）。

In Windows， programming via simple port drivers will lead to the usual latencies like the well-known I/O programming of the parallel port. In this respect， ATA I/O could be seen as a substitute for the good old parallel port， which is lacking on nearly all contemporary commercial-grade motherboards （at least in small form factors）。 However， if the latencies are to be avoided， the entire I/O part of the application program must be written as a kernel driver.

FUNCTION BLOCKS
Because you want to support the development of truly application-specific I/O adapter hardware， it is advantageous to distinguish between the ATA side and the application side of the adapter circuitry （see Figure 2）.Obviously， the circuitry that connects directly to the ATA interface could be some kind of standardized function block. This function block is called the ATA front end. Figure 5 shows the function block together with the application-specific inputs and outputs and the corresponding address decoding circuitry. Output data is held in registers. Input signals do not require particular registers because the front end contains a common Read data register. Hence，they can be attached via a data selector.

Figure 5-This ATA I/O adapter is based on a front-end function block. The read data lines are attached via data selection circuitry. Address decoding, data selection (e.g., by means of multiplexers), and output registers are application-specific.

The front end contains the DH register，the data paths， and the basic decoding circuitry （see Figures 6 and 7）。The principle of operation will be explained by referring to the corresponding Boolean equations.


A PIO access according to the ATA standard should be executed if there is no DMA access and if the selection lines CS1- and CS0- are high and low，respectively （see Table 1）：
GENERAL_ACCESS =!DMARQ *
DMACK - * CS1 - * !CS0-

The DH register is accessed if PIO access has been initiated and if the DH register is selected via the ATA address lines：
DH_ACCESS = GENERAL_
ACCESS * DA2 * DA1 * !DA0

The ATA I/O adapter has been selected if the device address bit in the DH register matches the master/slave configuration：
DEVSEL =DH4 * SLAVE_SELECT+!DH4 * !SLAVE_SELECT=DH4 xnor SLAVE_SELECT

A common access-enable signal for the other four supported ATA registers will be asserted if a PIO access is executed，if the ATA I/O adapter has been selected， and if the current access does not address the DH register：
GEN_REG_ACCESS = GENERAL_ACCESS * DEVSEL * !DH_ACCESS

If a read access with a valid port address is executed， the ATA data bus driver is to be enabled as long as the read strobe line is asserted：
READ_ENABLE = GEN_REG_ACCESS * READ_ADRS * !DIOR

The decoding of the particular I/O port register addresses is left over to the application-specific circuitry. The READ_ADRS signal has to be activated by the application-specific circuitry. It should be active if the current port address in the DH register is a valid port address of the particular ATA I/O adapter （selective addressing）。

I highly recommend that you design the address decoders carefully. Socalled alias addresses （caused by incomplete or sloppy address decoding） are to be avoided. Each ATA I/O adapter should react only on valid addresses.

DATA PATH STRUCTURE
Because CPLDs do not support tristate buses， separate read and write data paths have to be provided. Write data are propagated from the ATA data bus to the internal write data bus. Read data are clocked into the synchronization register and driven onto the ATA data bus.

THE NEXT STEP
In contemporary PCs， ATA is the last remaining low-latency interface providing a straightforward hardware/softwar API. Designing appropriate adapter hardware is comparatively easy. It requires nothing more than a small CPLD-and a few gotchas to be considered. ATA I/O adapters have been attached to all kinds of PC motherboards. Besides the obvious application of using up legacy hardware， it is especially compelling to apply such adapters together with miniaturized motherboards of the commercial high-volume market， such as Mini-ITX， Nano-ITX， and Pico-ITX. Supporting Serial ATA （SATA） will be the next logical step.

Wolfgang Matthes （w.matthes@t-online. de） has developed peripheral subsystems for mainframe computers and conducted research related to specialpurpose and universal computer architectures for the last 20 years. He has also taught Microcontroller Design， Computer Architecture， and Electronics （both digital and analog）at the University of Applied Sciences in Dortmund， Germany， since 1992. Wolfgang‘s research interests include advanced computer architecture and embedded systems design. He has filed over 50 patent applications and written seven books.

PROJECT FILES
To download code and schematics, go to ftp://ftp.circuit cellar.com/pub/Circuit_Cellar/2008/214.

RESOURCES
W. Matthes, "ATA Interface Misused,"Elektronik, 2006.

---, "Input/Output Device for Attachment to a Drive Interface,"German patent application DE 10 2005 002 339.8.

The ReAl Computer Architecture,www.realcomputerarchitecture.com.

Technical Committee T13 AT Attachment,"ATA Standards," www.t13.org.

SOURCE
XC95108 CPLD
Xilinx, Inc.
www.xilinx.com