Create a Signal Source for a Variety of RF ApplicationsNeal describes how he built an inexpensive and accurate
variable-frequency signal generator on a two-sided PCB. The system
delivers frequencies from 0 to 3 GHz with a frequency accuracy of
less than 200 Hz.
If you pursue designs that take you into the world of radio
frequency （RF）technology， you may need a stable，high-frequency
signal source. If you are interested in a quality source that won‘t
break the bank， read on.
Last fall， I began working on a project involving high-frequency
narrow-band frequency shift keying. The project required several
stable， high-frequency signal sources located at multiple physical
locations simultaneously. Rather than build several narrowband
sources or purchase a number of expensive wideband sources， I
decided to build a variable-frequency stable source that was
general-purpose， accurate，and affordable.
The goal for the RF signal generator was for it to deliver an
operator-selected frequency from 0 to 3 GHz with a frequency
accuracy of less than 200 Hz（see Photo 1）。 The targeted output
power level was 10 dBm， with a phase noise specification of -80 dBc
at a 10-kHz offset. My other goal was to keep the harmonic levels
greater than 40 dB below the fundamental. To control costs， I
decided to implement the design on a single two-sided PCB，including
the power supply.
Many of these design goals were met or exceeded. Some are
still"works in progress." I think you will agree that this design
will serve as an excellent signal source for many RF applications.
ARCHITECTURAL TRADE-OFFSA phase-locked loop （PLL） is an obvious choice for controlling
frequency in signal generator designs. But a PLL alone does not
work in this application.
Look at the dotted-line box in Figure 1. These are the primary
elements of a typical PLL. It contains a voltage-controlled
oscillator （VCO）， a PLL controller，and a loop filter. Typically， a
fixed-frequency clock provides a stable reference for the PLL
control chip. The PLL output frequency is controlled by setting the
values of the"R" and "N" dividers. Once the dividers are set up，
the control chip compares the reference clock （FREF）
divided by R to the VCO output （FVCO）divided by N. The phase
detector in the controller compares the two divided- down signals
and generates an error signal proportional to the difference in
frequencies. The error signal is filtered by the loop filter and
drives the VCO until the PLL locks：
The equation for the VCO output frequency is：
点击查看Figure 1
I considered only an integer PLL for this design. With an integer
PLL， R and N can have only integer values. A fractional PLL allows
fractional values for N， but it has a noisy output spectrum and is
not yet ready for prime time at these frequencies. Because R and N
are integers， the size of the PLL‘s frequency steps is determined
by the rate that the phase comparison is done in the PLL
controller. This rate is called the phase detect frequency （PDF）：
N has to be large to take small frequency steps， but there are two
problems with this. First， the selected PLL control chip determines
the maximum size of N. For the chip I selected， the maximum N is
524，288. With a 3-GHz VCO， N = 524，288 results in a minimum
frequency step of 5，722 Hz. Even if the control chip had a larger N
value， there is a more compelling limitation. It turns out that the
noise from sources in the PLL （reference， phase detector， and loop
filter） are increased by a factor of 20 log N decibels. This says
you want to keep N as small as possible. Another factor that says
you want N to be small and PDF large is that the PLL‘s closed-loop
bandwidth can be increased as the PDF increases. Increasing
bandwidth makes for a responsive PLL.
I had a problem！ I wanted a small PDF （large N） for small frequency
steps and a large PDF （small N） for low-noise signals and good
bandwidth. Faced with this problem， I went to the Internet to find
how others solved the problem. （Refer to the References section at
the end of this article.） There， I found an excellent
have-my-cake-and-eat-it-too solution. Using direct digital
synthesis（DDS） technology to precisely vary the FREF term in
Equation 2 was the answer.
ARCHITECTUREDDS technology gives you the ability to generate sampled sine waves
whose frequencies can be digitally controlled in small， precise
steps. In fact， if DDS was available up to 3 GHz， it could be a
good stand-alone solution in this application， but the technology
isn‘t there yet.
The best way to explain how DDS is applied here is with an example.
Assume that the reference clock FREF into the PLL is 10 MHz. Also
assume you want to use a PDF of 1 MHz， which enables you to have
relatively small N values. Setting the PDF to 1 MHz establishes the
PLL step size at 1 MHz. With PLL steps of 1 MHz， you need a way to
get the generator to produce the frequencies between PLL steps.
Refer to Equation 2. This can be accomplished by varying the FREF
term. So， if you vary the FREF frequency in small steps，you vary
the VCO output frequency in small steps as well. In my
example，let‘s say you have R and N set up to generate a 3-GHz
signal. Therefore，with a PDF of 1 MHz， R = 10， and N = 3，000.
Keeping R and N fixed and increasing the FREF by， say， one to
10，000，001 Hz， you get：
This is a frequency step size of 300 Hz at 3 GHz. As it turns out，
you can get much smaller FREF steps using DDS（0.014 Hz）， which
yields much smaller VCO output steps （4-Hz steps at 3
GHz）.Consequently， I have what I want：small， precise step sizes
using DDS and excellent output noise performance using a large PLL
PDF.
Now let‘s consider the RF generator's flow diagram shown in Figure
1， starting with the PLL enclosed by the dashedline rectangle. To
simplify the design，I cover as much of the desired output spectrum
with a single VCO. Here I employ a wideband VCO that produces a
sinusoid with a frequency of 1.3 to 3.2 GHz. The output of the VCO
is fed back to the PLL controller. This feedback signal is divided
by N and then compared to the input reference clock divided by R，
as described earlier. The controller‘s error signal output is then
filtered by the loop filter to drive the VCO. When the loop locks：
The VCO also feeds an RF buffer amplifier， which delivers the
desired output levels.
The FREF input to the PLL is provided by the DDS generator. The DDS
section consists of a fixed-frequency input clock，a DDS
generator chip， and an output filter. A 10-MHz clock is input to
the DDS controller and is multiplied by the DDS control chip to
develop a 60-MHz internal system clock. The DDS controller
generates a sampled sine wave whose frequency is a function of the
value in the controller‘s tuning word. The sampled sine wave is
internally converted to analog via a 10-bit high-speed DAC. The
nominal frequency generated by the DDS is 10.7 MHz. （I'll explain
the reason for this frequency later.） But the exact frequency
varies from the nominal 10.7 MHz by an amount required to microstep
the output of the VCO.
The raw output of the DDS controller is not a clean sine wave.
Because the signal is inherently a sampled sine wave，standard
Nyquist criteria apply. Consequently，there are a variety of alias
components that need to be filtered out. That is the function of
the 10.7-MHz filter located at the output of the DDS controller. It
should be noted that as long as the DDS signal falls within the
bandwidth of the filter， it will pass intact. Therefore， the
allowable output frequency range for the DDS controller is 10.7 MHz
±7.5 kHz. As I will explain， this is adequate for varying the FREF
to the PLL enough to cover the frequency gaps between the available
steps in the PLL.
The rest of the flow is fairly straightforward. The microprocessor
controls all of the registers in the chips， the keypad is used to
input frequency settings， and the LCD is used to display the
current state of the generator. A 5-VDC regulator and a 16.5-VDC
regulator are included to generate the needed DC supply voltages.
HARDWAREA schematic of the RF signal generator is shown in Figure 2. The
PCB is shown in Photo 2.
点击查看Figure 2You want a VCO that covers a wide frequency range. A single VCO
that covers 0 to 3 GHz is not available. So，I selected a
Z-Communications V600ME10-LF， which operates from 1.3 to 3.2 GHz.
It was chosen for its wide frequency coverage and because it
operates off a 5-V power supply. It＊s specified output level is 7.5
dBm 3.5 dBm，which is sufficient to deliver the power levels I want.
Its phase noise specification is -89 dBc at 10 kHz offset，which
meets my stated goals. The VTUNE input that controls the VCO＊s
frequency has a range of 0 to 20 V.
I used an Analog Devices ADF4113HV PLL control chip. I picked it
because it operates from 200 MHz to 4 GHz. More importantly，
however， this relatively new component from Analog has an internal
highvoltage charge pump. This eliminates the need for an external
op-amp at the output of the control chip， which is normally
included to convert the low-voltage charge pump signal to a level
high enough to drive the VTUNE control line of the VCO.
There are five components （R17，R18， C26， C27， and C28） that make up
the PLL loop filter. The filter＊s main purpose is to take the
current pulse error signal generated by the PLL control chip and
generate a clean proportional DC voltage to the VCO＊s VTUNE control
line. This filter affects loop stability， loop BW， and the overall
PLL output noise. There are textbooks that describe how to design
these filters. Fortunately， there are online resources available to
help with the heavy lifting. I used the ADIsimPLL tool from Analog
to design the filter for this application. Because I used an Analog
PLL control chip， I just needed to input the specifications of the
Z-Communications VCO and the phase detector frequency I wanted. The
ADIsimPLL did the rest. It output a schematic and open- and
closed-loop transfer plots， step response plots， and a variety of
other performance data. Some examples of the output of the tool are
shown in Figure 3. The resulting PLL designed using this tool has a
bandwidth of 19.5 kHz and an output phase noise of -81 dBc at a
10-kHz offset （assuming an ideal reference clock input）.
点击查看Figure 3On the output side of the VCO， a network of resistors is used to
feed back the output signal to the control chip. The network
interfaces the VCO to an output RF amplifier. When working with RF
frequencies， make sure that the loads seen by devices like the VCO
are 50 -。 This minimizes the effects of source/load mismatches like
power level variations and frequency shifting. Attenuating the
output is a technique used to minimize mismatch effects. In
addition， you need to feed back the VCO＊s output to the ADF4113HV.
However， the feedback signal must be in the range of 0 to -10 dBm.
Attenuation of 12 dB solves both problems.
The 12-dB attenuation is accomplished by using resistor pads.
Figure 4 shows how the resistor network is constructed. The network
consists of two 6-dB T pads in series. Each pad has an input and
output impedance of 50 -。 Consequently， the z1， z2， and z3
impedances in Figure 4 are all 50 -（this assumes that the amplifier
input is 50 -）.
Assuming the VCO output is at 7.5 dBm （0.54 VRMS），and doing the
voltage divider math， you will see that the signal level at the
50-Ω resistor that feeds back to the PLL RFIN is 0.133 VRMS. This
corresponds to a -4.5-dBm signal level required by the ADF4113HV
PLL chip. The same is true for the signal level into the RF buffer
amplifier. Assuming I have the nominal REFIN clock input to the PLL
of 10.7 MHz and that I want to have a nominal PDF of 1.07 MHz， I so
far have a stable， low-noise PLL with a frequency step size of 1.07
MHz. Next， I need to microstep the REFIN clock so I can have the
PLL generate frequencies between the 1.07-MHz steps. If you examine
Equation 2，REFIN must be able to vary over a range of ±3，578 Hz to
microstep within the 1.07-MHz PLL step. The finer the REFIN steps，
the better the output resolution. Now let‘s examine how this is
done with the DDS portion of the schematic.
The heart of the DDS circuit is the AD9851 DDS synthesizer chip. It
takes a 10-MHz CLK IN， multiplies the frequency by six， digitally
synthesizes a sine wave， and D/A converts it to generate a sinusoid
with precise frequency control. The equation controlling this
device is：
AD9851 output frequency = （Tuning Word） （6） （CLK IN）/2
32The Tuning Word is 32 bits long， so high resolution is possible.
With a 10-MHz CLK IN， the AD9851 frequency step size is 0.014 Hz. A
0.014-Hz step size in the DDS corresponds to an RF generator output
step size of less than 4 Hz over the full operating range of 1.3 to
3.2 GHz. That's excellent frequency resolution！
The AD9851 is a digitally sampled waveform generator， so it has
several components in its output spectrum that you need to clean
up. That is why the AD9851 is followed by a narrowband crystal
filter. The filter‘s bandwidth is wide enough to pass the signal
over the ±3，578-Hz variations required for microstepping， but it is
narrow enough to eliminate the undesired components of the AD9851
sampled waveform. An inexpensive 10.7-MHz crystal filter was
selected for this function， and it is the reason why the nominal
reference frequency to the PLL was set at 10.7 MHz.
The input impedance of the crystal filter is nominally 3，000 Ω/2
pF， and it is driven from a 50-Ω source， so an impedance-matching
network is required. Crystals are sensitive to having their input
and output impedances matched to deliver their specified filtering.
An LC network is used to accomplish this matching. The L and C
values were determined using an online tool. （Refer to the
References section at the end of this article.） The tool called for
L = 5.7 μH and C = 38 pF. Taking into account stray capacitance，the
2 pF of internal capacitance at the crystal input， and the standard
values available， the values of 33 pf and 5.6 μH were selected. How
do these small components match a 50-Ω source to a 3，000-Ω load？ An
intuitive explanation is that the shunt capacitor is there to lower
the crystal‘s 3，000-Ωinput impedance to 50 Ω， and the inductor is
included to cancel out the reactive component introduced by the
capacitor. Mathematically， if you look at the impedance of the
shunt capacitor（38 pF） and the 3，000-Ω crystal input in parallel，
you get：
So， if you get rid of the -385j reactive term， you will have the
50-Ω impedance you want. To do this， because the inductor's
impedance adds in series with the above Z， set jwL = 385j， yielding
L = 5.7 μH. This leaves you with the desired 50-Ω impedance.
Incidentally，the beauty of impedance matching with an LC is that
you also get some additional filtering at 10.7 MHz. There is also
an LC at the output of the crystal， but it is not there for
impedance matching because the crystal is driving a 3-kΩload. It is
simply an LC tuned to 10.7 MHz （it takes into account the 10-pF
input impedance of the ADF4113HV） to provide additional filtering.
I chose a Microchip Technology dsPIC30F3010 microprocessor because
it is fast， it has an internal clock， it has enough memory to allow
for C programming （including stdio functions）， and it has enough
I/O pins to satisfy the design. Plus， I had a few left over from
another project. I wanted to make sure I had plenty of bandwidth to
expand the functionality of the RF generator in the future. The
microprocessor controls all the registers in the ADF4113HV and the
AD9851， and it performs all of the calculations using high-speed
integer arithmetic. The interfaces to the keypad and LCD are also
handled by the microprocessor.
I used an ADP3339 low-dropout regulator to generate the 5-V supply.
It is a good solution because it can provide all of the necessary
power without any heatsinking. The ADF4113HV also requires an
available low-current 16.5-VDC regulated supply. I generated the
supply with a MAX5026 DC/DC converter. It takes the 5 V available
from the main supply and generates 16.5 V of clean output. The
16.5-V output is determined by the values of R1 and R2. The 16.5-V
level covers the tuning range of the VCO while not exceeding the
maximum level allowed by the ADF4113HV high-voltage charge pump
supply.
RF LAYOUTThere are a few layout considerations to think about when building
RF circuits. Pay close attention to supply bypassing. Suppliers of
RF components will typically suggest capacitor values， SMD
component sizes， and， in some cases， even tell you how close the
bypass capacitor needs to be to the pin you are bypassing. It is
also good practice to return all ground connects to ground with
separate vias. In other words， if you have several pins on an IC
that need to be grounded， connect them to the ground plane with
their own via to avoid any subtle interactions.
In this two-sided design， the bottom of the PCB is almost
completely a ground plane. It is not a single plane. Instead， it is
three separate planes connected to the power supply ground at a
common point. This "star" configuration of the ground plane helps
keep the different sections of the circuit from interacting via
unwanted ground loops.
Finally， there are those who will disagree with me on this， but if
you keep your high-frequency traces short （less than 0.1× the
wavelength）， you don‘t have to be too concerned about having PCB
trace widths designed to yield a 50-Ω loading. You are better off
if you keep things short and match the trace width to the SMD parts
you are interconnecting.
FIRMWAREI have been using C to program my past few projects. It was a
little painful coming up to speed， but now I am a real convert.
Using C enabled me to do 64-bit integer arithmetic with ease and
gave me access to some built-in functions that were extremely
useful. The sprintf built-in standard I/O function， for example，
lets you easily create a formatted ASCII array， making formatted
LCD output quite simple. For example:
sprintf（Array，"Frequency = %u Hz"， Fvco）；
The sprintf statement is all that is needed to have the LCD read
"Frequency = 300 Hz，§ assuming FVCO is 300 at the time the command
is executed.
Likewise， the standard I/O function sscanf lets you go the other
way by taking formatted ASCII input and converting it to numerical
values. This is extremely useful when you are inputting keypad
values that you want to convert to numbers.
If you are tired of rewriting LCD and keypad interface programs
because you are using different I/O pins on the microprocessor，
look at the C code in this project. You don＊t have to rewrite the
two programs for future projects. The two programs are written in
such a way that you have to change only the pin assignments in the
header files and you＊re set to go. For experienced C gurus， don＊t
be too critical of my C skills. As I said， I am coming up to speed.
HOW IS IT WORKING SO FAR？Take a look at how the RF generator performs. For operating at 3
GHz，the only instrument I have access to that shows the frequency
spectrum up to 9 GHz （to see harmonics） is an old Hewlett-Packard
141T/8555A spectrum analyzer. Be careful when looking at the output
of the analyzer because it uses harmonic mixing and displays the
resulting spectrum in a bit of a confusing manner.
Photo 3 shows the analyzer＊s output. Starting on the right， the
3-GHz fundamental is displayed. Moving left，the next line is the
second harmonic at 6 GHz. The next left line is the third harmonic
at 9 GHz. The other lines on the display are just the same three
components that were shifted into the display spectrum by harmonics
of the internal local oscillator. Consequently， they can be
ignored. The analyzer was used to check the output levels because
the frequency of the RF generator was varied.
The results show the output level is consistently between 8 and 10
dBm as the frequency is varied from 1.3 to 3.2 GHz. Also， the
second and third harmonics are typically at -42 dBc and-54 dBc，
respectively.
I tested for frequency accuracy by connecting the output of the RF
generator to a 3-GHz universal counter that is sensitive enough to
detect signals as low as -15 dBm. I was pleased with the results.
To have the exact output frequency， I had to add the capability （in
the firmware） of inputting （via the keypad） the actual frequency of
the clock into the AD9851. A 1-Hz error assumed for this clock
results in an output error of 280 Hz at 3 GHz and 140 Hz at 1.5
GHz. In retrospect， I should have used a higher-quality
temperature-compensated part for the clock into the AD9851. The
part I used required me to measure the clock more often than I
wanted for an exact frequency output. With that said， once the
actual AD9851 input clock was measured and input， the frequency was
accurate to less than 4 Hz over the full range of frequency. I
found that impressive！
FREQUENCIES BELOW 1.3 GHz
At this point， you might be saying：※Wait a minute！ I thought you
said the generator was capable of generating signals from 0 to 3
GHz. So far， I see only 1.3 to 3.2 GHz.
Look at Photo 1 to see how the lower frequencies are obtained. Two
RF generators （one in an enclosure and one with only the PCB） are
plugged into an off-the-shelf passive RF mixer（Mini-Circuits
ZX05-43LH）。 One generator provides the RF input to the mixer and
the other serves as the local oscillator. The third port is the
intermediate frequency （IF） output，which contains， among other
things，the difference frequency that is the desired signal. For
example， if one generator is set at 2 GHz and the other is set at
2.3 GHz， the generated difference frequency will be 300 MHz.
Because I was now much lower in frequency， I was able to use a
modern spectrum analyzer to look at the resulting spectrum. The
output spectrum of the RF generator is shown in Photo 4. For
comparison， you can see the output of an expensive signal
generator， also generating a 300-MHz signal.
Photo 4 shows that the harmonic levels of the RF generator are not
down as far as the expensive generator，but they are still
relatively low. The second harmonic for the RF generator is down 45
dB. To put this in perspective， say you have a 10-dBm（0.71 VRMS）
fundamental. The unwanted second harmonic would be-35 dBm （0.004
VRMS）。 That is a small distortion.
There are other frequency components in the RF generator＊s output
spectrum. Unlike the previous example where the spectrum analyzer
caused the extra spectral components， the components are real and
result from the mixing process. Besides the normally expected sum
and difference frequencies generated when mixing， output components
are generated by the harmonics of the local oscillator and
harmonics of the RF input signal. The location of the components is
calculated by the equation n × FLO ± m × FRF. Using this equation，
Table 1 shows the location of these components for the 300-MHz
signal that＊s generating. As you can see in Photo 4， the components
are located exactly where the table predicts they should be. Again，
the components are still down at least 40 dB from the fundamental，
which is just fine in most cases. If you generate this 300-MHz
signal by mixing a 2.7-GHz signal with a 3-GHz signal， none of the
components of n ℅ FLO m ℅ FRF would be seen in the displayed
spectrum because they would fall outside the frequency range
displayed by the spectrum analyzer.
Note that there are also attenuated versions of the RF and local
oscillator signals that leak through any mixing process. They are
usually attenuated by greater than 30 dB and can be filtered out by
low-pass filtering if your application requires it. They do not
appear in Photo 4 because they fall outside the frequency range
displayed by the spectrum analyzer.
Frequency accuracy and signal levels are important， but the quality
of the output signal in terms of noise is more important. Photo 5
shows a closer frequency look at the fundamental for an expensive
signal generator and my RF generator side by side.
At a 100-kHz offset from the fundamental center frequency， the
noise level is comparable. But below 100 kHz， the expensive
generator is less noisy. This really bothered me when I first
observed it until I figured out why this was happening. It turns
out that the source of this added noise in the RF generator is the
clock source I used for the AD9851. The part was specified to have
phase jitter less than 1 picosecond. I thought this was excellent
at the time； but after precise measurements， I found that the
clock＊s phase noise was -80 dBc at a 10-kHz offset. If you put that
into the ADIsymPLL tool， the results shown in Photo 5 are exactly
what is predicted. Using a part with a phase noise of -110 dBc
would reduce the nose levels of the generated signal for offsets
below 100 kHz. A part like this is not a simple drop-in
replacement；however， because this kind of clock chip comes with a
0.8-VPP output，an additional chip is needed to convert to the CMOS
level required by the AD9851. This is the work in progress that I
mentioned at the beginning of the article.
WHAT‘S NEXT
Besides adding a better AD9851 clock source， I intend to add FM
modulation code to the generator's feature set. With a 30-MIPs
processor， a 19.5-kHz PLL bandwidth， and a 3.3-MHz update rate for
the DDS chip， there is plenty of horsepower to FM-modulate the
signal.
Currently， I use off-the-shelf Mini- Circuits attenuators to vary
the output signal level a fixed amount. They connect directly to
the RF generator‘s output. But for more flexibility， I am also in
the process of designing a separate PCB to accomplish output level
control and AM modulation. In addition to having its own
microprocessor and supply， it will use a variable-gain RF amplifier
and RF log detector in a closed-loop system.
This project was fun. It caused me to learn new things and
ultimately yielded a high-precision RF signal source. That's what
keeps me coming back for more！
Neal Martini （nealmartini@cableone. net） holds an M.S.E.E. from the
University of Missouri， Rolla. He is retired after 24 years of
working for Hewlett-Packard in the LaserJet and InkJet printing
businesses. In addition to being involved with a variety of boards，
Neal works independently in product development in several
application areas. In his spare time， he enjoys spending time with
family，woodworking， racquetball， golf， and playing the piano.
PROJECT FILESTo download code, go to
ftp://ftp.circuitcellar.com/pub/Circuit_Cellar/2008/219.
RESOURCES
"L/C Impedance Matching Network Design Tool,"
www.hoflink.com/~mkozma/match19c.html.
P. Nelson, "PLL Combines With Digital Synthesis," EE TIMES,
September 2003.
S. Sprowls, "Scotty's Modularized Spectrum Analyzer Web Site,"
www.scottyspectrumanalyzer.com.
SOURCESAD9851 DDS Synthesizer,ADF4113HV charge pump, ADIsim-PLL software,
and ADP3339 lowdropout regulator
Analog Devices, Inc.
www.analog.com
141T/8555A Spectrum analyzer
Hewlett-Packard
www.hp.com
dsPIC30F3010 DSC
Microchip Technology, Inc.
www.microchip.com
ZX05-43LH Frequency mixer
Mini-Circuits
www.minicircuits.com
V600ME10-LF VCO
Z-Communications, Inc.
www.zcomm.com
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