The roots of Altera‘s MAX II go back about 30 years to the
programmable array logic （PAL）device. This month， Tom covers the
history of programmable logic chips and introduces you to MAX II
technology. Say hello to his little friend.
In this the twentieth year of Circuit Cellar magazine， I find
myself contemplating new developments in the context of history.
Like they say， you can‘t know where you are if you don't know where
you started.
This month， let‘s look at a chip whose roots go back three decades
to a chip called the programmable array logic （PAL）。 The PAL wasn't
the first programmable logic chip per se， but following a bit of a
rocky start， it became the first to make a big splash in mainstream
applications.[1]
These days， programmable logic chips go by different names， such as
CPLD or FPGA； but ultimately，the benefit proposition is basically
the same as it was way back when-to wit， the opportunity to roll
your own chip.
I say we bring back the PAL moniker. I mean，CPLD and FPGA don‘t
exactly roll off the tongue， do they？ And what could be better from
a warm and fuzzy branding perspective？Let‘s hear it system
designers， who's your buddy？
Whatever you call them， like all things silicon， programmable logic
chips have marched to the tune of Moore‘s Law. They've lagged
behind the parade a bit compared to more generic parts like DRAMs
and MCUs； but nevertheless， they‘re light years ahead of the
original PALs.
But what matters to designers isn't whether a particular chip
delivers more for less over time. That just means everything gets
cheaper， but it doesn‘t necessarily change a designer's perspective
in terms of what chips to use for what applications.
Programmable logic chips cover a huge spectrum from $1 to thousands
of dollars. Towards the high end， the implications for designers
are clear. The situation is pretty much summed up with the phrase
"ASIC refugees." If you‘ve been designing ASICs， chances are at
some point （if not already）you‘ll be switching to FPGAs.
At the low end， the situation is less clear， which inspires this
month's contemplation. Can programmable logic chips penetrate
mass-market applications by supplementing or even displacing
standard chips？ To what degree， how soon， and in what apps？
Let‘s take a look at a latest and greatest descendent of our old
PAL and see just where we stand.
YOU SAY TOMATO
I suppose it's best to get the buzzwords out of the way right up
front. Altera calls their MAX II a "CPLD，"which is presumably
deemed to be more "complex" than a regular"PLD." But depending on
how you look at it， it‘s really a "PAL on steroids" or an "FPGA in
drag."
Like the original PAL， the MAX II is a self-contained， single-chip
solution. Furthermore， it‘s pitched for pin-centric"control-path"
（i.e.， high pins/ logic ratio， low pin-to-pin delay） applications
just like the PALs of yore.
Cars are still measured by "horsepower"even though nobody rides a
horse. Along the same lines， MAX II chips are still ranked in terms
of PALera"macrocells，" a combination of OR and AND gates
（sum-of-products）and some I/O （e.g.， flip-flop）。 Of course， there
are a lot more macrocells these days. The original PAL had eight，
while the MAX II line-up runs from 100s to 1，000s （see Table 1）。The
irony is that under the hood the MAX II is really an FPGA， indeed
using exactly the same SRAM-based look-up table （LUT） logic fabric
as Altera‘s Cyclone FPGAs. The "macrocell"count is just an estimate
based on an empirical FPGA logic element（LE） to "macrocell
equivalent" conversion factor. MAX II isn‘t actually "live at
power-up" like the original fusebased PAL， but it's the next best
thing with on-chip flash eliminating the need for an external
memory chip to store the configuration.
Altera got their start with PAL-like（i.e.， true macrocell
architecture） chips and still offers them today （e.g.，MAX3000 and
MAX7000）。But the showstopper for the traditional macrocell approach
is that it doesn‘t scale up well. The
"everything-to-everything"interconnect strategy selfdestructs（more
wires， more power，less logic utilization） as macrocell count climbs
into the 100s and beyond. In short， the original PAL architecture
has just outgrown its silicon britches.
VOLTSWAGEN
The MAX II comes in three flavors：regular， "G，" and "Z." Under the
hood， they‘re all basically the same（i.e.， Cyclone FPGA logic）。 The
main differences are power related. That's important， because
historically， programmable logic hasn‘t been known for being
especially "green" or suitable for battery-powered applications.
The entire line-up is based on a 1.8-V internal core supply， but
the regular MAX II parts offer the convenience of an on-chip
voltage regulator to run off an external 3.3- or 2.5-V supply. The
MAX IIG just dispenses with the regulator to run from a 1.8-V
supply directly， which significantly reduces power consumption.
Same for the MAX IIZ， which also has a special provision for "zero
power" applications，as we'll see later. Note that the"Z" option is
only offered for the two smaller parts （‘240 and '570） and comes
with a performance hit （clock rate and propagation delay）.
I/O wise， all of the parts are versatile，supporting the usual I/O
suspects，as shown in Figure 1. There are some caveats though. The
two larger parts（‘1270 and '2210） feature four separate I/O banks
versus two banks for the smaller parts. More banks are not only
useful to support more different interfaces，but they also offer
more flexibility in terms of granularity. For example，with four
banks， you can run three-fourths of the pins at one level and
one-fourth of them at another，something that isn‘t an option with
just two banks.
Along the same lines， only the two larger parts offer PCI
compatibility because the smaller parts don't have enough logic
capacity to support that interface. The implications go further
than just PCI because the PCI I/O capability provides a means
（i.e.，clamp diode） for the larger parts to handle 5-V TTL or CMOS
I/O with the addition of an external resistor or two. The smaller
parts might be able to output to a 5-V TTL chip （presuming the MAX
II 3.3-V output meets the TTL chip VIH minimum spec）， but that‘s
about it.
As for packaging， there are three basic options， including TQFP，
"fine line" BGA （1-mm pitch）， and the latest"micro fine line" BGA
（0.5-mm pitch）。 Pin counts range from 68 all the way to a whopping
324 pins. Understandably， not every part is offered in every
package with the lower pin-count packages naturally biased towards
the parts with less logic and higher pin counts towards those with
more logic.
The "micro fine line" packages stand out by cramming a lot of I/O
into a little board space. Make that"Lot" and "Little" with a
capital "L."For example， TQFP parts consume about 3 mm2 of board
area per pin while the micro fine line turns that spec on its head
by packing about three pins per mm2. For example， compare the
144-pin TQFP at 484 mm2 with the 144-pin micro fine line BGA at 49
mm2. That‘s a factor of 10 higher density！ With 144 pins in a
package，barely more than 0.25″ on a side，make sure you bring a
magnifying glass.
The tiny packages are great for your size-constrained applications.
But how about the unlucky engineer who gets assigned to do the PCB
layout？Fortunately， Altera offers a detailed app note on doing just
that.[2] More layers to work with no doubt make the job easier， but
the app note does show that it is possible to do a layout using
just two signal layers （plus power and ground planes）.
JAM SESSION
Ignoring the FPGA innards， as described so far， the MAX II is kind
of like a 1970s PAL， just one where every spec is improved. But
that‘s only the start. The MAX II not only does everything a PAL
did better， but it also does a lot of new stuff too.
Most of the new capabilities are thanks to the onboard flash
memory. The original PALs were fuse-based and thus only one-time
programmable in a production-line setting. By contrast，the MAX II
configuration is reprogrammable，even in-system during normal
operation. Better yet， the configuration flash memory （CFM） is
supplemented with an additional 8 Kb of user flash memory （UFM），
which， as the name implies， is available for your own application
data.
First， let's discuss the CFM. Flashing the MAX II （i.e.，
programming the CFM） is accomplished by feeding the chip a
bitstream through dedicated JTAG pins. The scheme relies on a JEDEC
Standard Test and Programming Language （STAPL） known as "Jam."
During development， the PC and the Altera tools （i.e.， Quartus II
software and JTAG download cable） handle all of the programming
details behind the scenes. But if you want to do in-system
configuration， your design needs enough smarts to host its own "Jam
Player" （i.e.， device programming software），as well as room to hold
the MAX II configuration data itself （"Jam Byte Code" aka "JBC"）.
The Jam Player is written in "C" for easy porting， a process that
boils down to mapping your hardware connections to the MAX II JTAG
pins and tweaking a delay loop for proper timing. But the
convenience comes at the cost of a sizeable memory footprint. An
example port running on a 68000 puts the toll at roughly 96 KB of
ROM and 48 KB of RAM.[3] Altera also has an app note using an 8051
for in-system programming， but it isn‘t pretty.[4] Limited memory
means the '51 can barely handle the smallest MAX II chips， and
limited MIPS make for long（as in many minutes） programming times.
Presuming a design has the smarts to handle in-system programming，
the MAX II deals with the gotchas. For instance， it‘s possible to
use a "realtime ISP" mode that has the flash memory updated in the
background while the existing configuration （i.e.，in SRAM）
continues to run. The new configuration will be downloaded to SRAM
at the next power-cycle or the download can be triggered
immediately with a JTAG command. An other option is to use an "I/O
clamp" feature that sets and locks the pin state during
reconfiguration. Note that the CFM is only accessible via JTAG and
has a security bit to keep designs safe from pirates.
The user flash memory can also be programmed via a JTAG， but it‘s
accessible by the application （i.e.， the MAX II logic fabric） as
well （see Figure 2）。 The native （clock serial） interface is pretty
straightforward and the chip handles the gory details of
programming sequence and timing.
The beauty of programmable logic is that you get to have it your
way. The Altera tools include IP megafunctions that front the MAX
II UFM with conventional interfaces （see Table 2）.Indeed， the user
flash could help the MAX II pay for itself if it can eliminate the
need for a standalone EEPROM chip. Just keep in mind there are some
operational differences. For instance， a true EEPROM is
byte-erasable while the MAX II UFM is only sector-erasable. And
before you get too excited， note the MAX II flash write endurance
spec is a mere 100 cycles. The MAX II has an on-chip oscillator
used for self-timing the flash operations. Altera had the foresight
to make the oscillator available to the logic fabric as well. Yes，
it‘s not especially accurate （runs anywhere from 3.3 to 5.5 MHz）
and may not be a big deal in most applications. But in certain
situations， an on-chip clock （even a sloppy one） can prove very
useful.[5] For example， Figure 3 shows an application using the
oscillator as the clock source for an automatic power-down timer.
Altera Zeros Out Power with New MAX IIZ CPLDs for Portable
Applications
"The devices...provide both high functionality and zero-power
consumption in a single device."[6]
We all know that the silicon era has been about， pun intended，
"Moore for Less." But it seems to me that"Something for Nothing，"
as in "zeropower consumption，" is pushing it.
Take a look at the MAX II dynamic power consumption graph in Figure
4. Not surprisingly， the regular MAX II chip burns more power due
to voltage drop from the external supply （e.g.， 3.3 or 2.5 V）
across the internal 1.8-V regulator. Running directly off a 1.8-V
external supply， the MAX IIG and IIZ naturally consume a lot less
power. But at the same time， there appears to be little power
saving advantage gained by choosing "Z" over "G." It is all the
more true considering that the "Z" performance specs （clock rate
and propagation delay） are quite a bit derated.
Rather， it‘s the standby power spec where the difference between
the parts is pivotal. Once again， the regular MAX II spec is high
（12 mA） due to the on-chip voltage regulator. Jettisoning the
regulator，the "G" consumes much less standby power （2 mA）。 But as I
mentioned earlier， every milliamp matters in battery-powered
designs. Here‘s where the "Z" parts shine with a 60×reduction in
standby power （less than 33 μA typical） compared to the "G"version.
That‘s up to 60× （and 360×compared to the regular MAX II）longer
battery life in applications that spend a lot of time in standby.
There is one caveat worth noting. The "Z" cuts standby power by
eliminating the on-chip voltage monitor（which also explains the
slightly lower dynamic power consumption of "Z"compared to "G"）。
The voltage monitor protects the MAX II and IIG during brownout
conditions by tri-stating the I/O and rebooting the configuration
when power stabilizes. With the "Z，"it‘s up to you to guarantee
that the power supply meets spec or otherwise deal with the
possibility of the chip freaking out if it gets stuck somewhere
between "on" and "off."
Of course， thanks to the "live at power-up" capability， simply
pulling the plug would seem a viable powermanagement option.
However， in a multi-chip system where some chips are powered and
some aren‘t， that scheme raises a variety of "hot socket"
concerns. Fortunately， the MAX II does a great job in this regard.
The chip can be driven before power-up，which itself can be any
sequence（VCCINT and VCCIOs）。 Pins are tristated until the power
supplies and internal configuration stabilize. The power supply
sections of the chip are isolated to prevent current leakage due to
activity on the signal pins of a de-powered （i.e.， VCCINT， VCCIO =
GND） MAX II.
Don‘t go overboard with cycling the power as a power management
strategy. Notably， power consumption during power-up configuration
（i.e.， copy from flash memory to SRAM） is a whopping 40 to 55 mA
for up to 200 to 450 μs depending on the specific part. Thus，
you'll have to consider the duty cycle of your application
（i.e.，how long the MAX II can remain powered off） relative to the
standby power specs of the particular part （microamps for "Z" and
milliamps for the others）
to decide if and when the power cycling option works best.
FRIENDS
There is no doubt that the MAX II is a vast improvement in every
way（price， performance， power， and package）over the PALs of yore.
But with everything shrinking into fewer chips，does anyone really
need "glue logic"anymore？ Maybe designers can go it alone and don‘t
need to bring a PAL along.
My take is that there are still applications for chips like the MAX
II， but they've grown up along with the silicon. In larger designs，
there remain plenty of chores where a friendly helping hand is
appreciated.
The ability of the MAX II to deal with up to four different I/O
voltage levels （banks） is a unique capability. Given the
combination of high pin count， high density， and low price（starting
at $1.25 in volume）， the chips would seem a natural for level
translation and monitoring in multivoltage designs.
The MAX II is bulked up with versatile I/O， but it‘s smart too. For
instance， say you've got a 3.3-V peripheral chip that needs to work
with a 1.8-V MCU. The MAX II can handle that. But what if the
peripheral uses an I2C interface but the MCU has a SPI port？ The
MAX II can handle that too by using the programmable logic to
implement an I2C-to-SPI adapter. T
he MAX II on-chip flash memory is a bonus that shouldn‘t be
overlooked. Together， the "live at powerup"and "in-system
programming"features combine to deliver the best of both the PAL
and FPGA worlds. And although not as robust as a true EEPROM（i.e.，
limited write endurance），the flash memory is a handy place to store
"once-in-awhile" updates such as configuration and calibration
data.
The combination of low-power operation and even lower power standby
means it finally makes sense to mention"programmable logic" and
"battery"in the same sentence. The "hot socket" features come into
play by allowing the MAX II to deal with whatever happens， and
whenever it happens， power-wise.
Sure we‘ll never forget our old PALs. But now that we've met the
MAX II， I think you‘ll agree it's time to move on and make some new
friends.
Tom Cantrell has been working on chip， board， and systems design
and marketing for several years. You may reach him by e-mail at
tom.cantrell@ circuitcellar.com.
REFERENCES
[1] T. Kidder, The Soul of a New Machine, Black Bay Books,
Boston,MA, 2000.
[2] Altera, Corp., "Application Note 114: Designing With
High-Density BGA Packages for Altera Devices,"2007, www.altera.com/literature/an/an114.pdf.
[3] ---, "Chapter 14: Using Jam STAPL for ISP via an Embedded
Processor," MAX II Device Handbook, Volume 1, MII51015-1.7, 2007,
www.altera.com/literature/hb/max2/max2_mii51015.pdf.
[4] ---, "Application Note 111:Embedded Programming using the 8051
& Jam Byte-Code, 2005," www.altera.com/literature/an/an111.pdf.
[5] ---, "Application Note 422:Power Management in Portable Systems
Using MAX II CPLDs,"2006, www.altera.com/literature/an/an422.pdf.
[6] ---, "Altera Zeros Out Power With New MAX IIZ CPLDs for
Portable Applications: Minimizes Power, Space and Cost," Press
Release, December 10, 2007,
www.altera.com/corporate/news_room/releases/releases_archive/2007/products/nr-maxiiz.html.
SOURCE
MAX II, MAX IIG, and MAX IIZ CPLDs
Altera Corp.
www.altera.com
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