“这是因为每个市场领域需求不同，”飞思卡尔CTO Lisa
Su说道。“在网络领域，我们从90nm直接进入到45nm时代，省略了中间的65nm。汽车电子领域则不同，现在我们依然再推许多90nm工艺产品，并且计划发展65nm工艺。消费电子领域也很难跳过某个工艺革新。虽然，网络领域也很难跳跃某个工艺环节，但是我们还是这样做了，接下来的22nm会是更艰难的一项挑战。不过我认为省略某项工艺与其说是技术问题不如将其归为企业市场定位。”
Moore’s Law continues progressing at a rate of one node every two
years or so, but the number of companies that are adhering to that
schedule is becoming much harder to pinpoint.
Even the nodes themselves are becoming fuzzy. While Intel is
looking at 32nm as the next node after 45nm, TSMC is looking at
28nm as the next node after 40nm. And there are likely to be
extensions within each node to allow some companies to stay on a
process node a lot longer than before.
Even within companies, there is no clear answer about when to move
to the next node. Freescale, which has been one of the die-hard
adherents to the relentless schedule of Moore’s Law, has recently
modified its stance. It follows the road map in some cases and not
in others.
“It’s different by market,” said Lisa Su, Freescale’s chief
technology officer. “In the networking market, we went from 90nm to
45nm. We skipped 65nm. In the automotive segment we won’t do that.
We’re doing a lot of 90nm products now and will move to 65nm. In
the consumer segment it is very hard to skip a node. If you’re in
the networking segment, it’s hard to skip a node but we did it.
22nm is going to be extraordinarily tough. I think skipping nodes
is more of a function of the market segment than the technology.”
Translation: It’s going to cost a bundle at each new node, and
companies are thinking very hard about what should be migrated and
when, where the various derivatives of those chips can be sold and
whether a platform approach will work to save costs.
“The lithographers were happy that they got some of the issues
solved (at 22nm), but it’s still going to be very expensive,” Su
said.
Consider that an understatement. The common thinking these days is
that for early adopters, the cost will be exorbitant. For one
thing, yield will vary because of process variability, which is
higher at each new node because of the complexity involved. At
22nm, foundries such as TSMC already are talking about restrictive
design rules and IBM is debating whether to actually reduce some
functionality at that node to save power and improve performance.
Intel says it has 22nm well under way, but exactly what will be in
its processors at that node has not been publicly disclosed.
Even the FPGA world is shifting its strategy. Actel, which has
built much of its business at 130nm, is moving to 65nm as its next
node. Rich Kapusta, Actel’s vice president of marketing and
business development, said the reason to stop there is that the
65nm process for that node is already well tested and variability
is low. Platforms, IP and other strategies
What is happening at Freescale and Actel is happening in many other
companies, as well. Decisions about cost vs. yield vs. market
opportunity are being discussed everywhere. In some cases,
companies decide to move to the next process node but stay at each
node longer. In others, they wait until it is absolutely necessary
to move to the next node, and then remain one step behind the
bleeding edge where the processes are already mature.
Platforms are another strategy that has crept into discussions.
Intel adopted its first platform when it introduced its Centrino
line of processors for laptop computers in 2003 after deciding that
multiple iterations of a single processor using different clock
speeds was inefficient. That same approach is now being applied to
both chips and the models being used to design those chips. Both
Mentor Graphics and Synopsys are pushing platforms, and IBM,
Samsung and Chartered Semiconductor have teamed up to create the
Common Platform for manufacturing.
The goal in each of these cases is to make work go farther than one
design to amortize some of the architectural and design costs.
Validated IP is another strategy that fits into that scenario. And
while all designs still need to be verified, with a platform
approach not all of the design has to be verified for each
iteration or derivative.
Tom Quan, senior director of EDA and design service marketing, said
Moore’s Law is flattening. The giant bell curve approach to a
process node is changing to reflect runaway costs and complexity
and the ability to recoup non-recurring engineering expenses. And
while the overall number of designs may not change significantly,
particularly in the SoC realm, the number at the most advanced
process nodes has already changed.
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