Lab 1 - Simple Hardware Design
Targeting XUP Virtex-II Pro PPC
Simple Hardware Design Lab: PowerPC Processor
Introduction
This lab guides you through the process of using Xilinx Platform Studio (XPS) to create a simple PPC processor system targeting the XUP Virtex-II Pro board. This lab will be used as the foundation for creating the remaining labs.
Objectives
After completing this lab, you will be able to:
• Create an XPS project
• Use Base System Builder (BSB) to create a system targeting the XUP Virtex-II Pro board
• Download the test application and verify output on hyperterminal
Procedure
The purpose of the lab exercises is to walk you through a complete processor system design. Each lab will build upon the previous lab. The following diagram represents the completed design.
Figure 1-1. Completed Design
In this lab, you will use the BSB of the XPS system to create a processor system consisting of the following processor IP:
• PPC405 (PowerPC processor)
• Proc_Sys_Reset (system reset circuitry)
• JTAG_PPC (interface to internal FPGA JTAG circuitry)
• DCM (Generates various clock frequencies used by the processor, busses, and peripherals)
• PLB bus (high-performance bus)
• PLB BRAM controller (PLB memory controller that connects to FPGA memory)
• BRAM (FPGA memory)
• PLB2OPB (bridge between PLB and OPB busses)
• OPB bus
• OPB UART Lite (lite version of the UART that is free with the EDK installation)
Figure 1-2. Processor IP
This lab comprises three primary steps: You will create a project using Base System Builder, analyze the project created, and generate the processor system netlists. Below each general instruction for a given procedure, you will find accompanying step-by-step directions and illustrated figures providing more detail for performing the general instruction. If you feel confident about a specific instruction, feel free to skip the step-by-step directions and move on to the next general instruction in the procedure.
Open the Project Step 1
Launch Xilinx Platform Studio (XPS) and create a project file in C:\xup\embedded\xupv2pro\labs\lab1 by using Base System Builder. Select the PowerPC™ processor, the processor clock frequency as 300 MHz, the bus clock frequency as 100 MHz, and FPGA JTAG as the debug interface.
Open XPS by selecting Start Programs Xilinx Platform Studio 8.2i Xilinx Platform Studio
Figure 1-3. Select Xilinx Platform Studio
Do not select Platform Studio SDK; this opens the Software Development Kit IDE.
Select Base System Builder Wizard and Click Ok
Figure 1-4. New Base System Builder-Based Project Creation
This opens the Create New Project Using Base System Builder Wizard dialog box.
Figure 1-5. Create New Project Using Base System Builder Wizard Dialog Box
Specify the Project File as C:\xup\embedded\ppc\labs\lab1\system.xmp and click <OK>
Select the I would like to create a new design option
Click Next to display the Select Board dialog box. Specify settings to match the following:
Board Vendor: Xilinx
Board Name: XUP Virtex-II Pro Development System
Board Revision: C
Figure 1-6. Select Board Dialog Box
Click Next to display the Select Processor dialog box
Figure 1-7. Select Processor Dialog Box
Select PowerPC as the processor
Click Next to display the Configure Processor dialog box. Specify settings to match the following:
Reference Clock Frequency: 100 MHz
This the external clock source on the board you are using. This clock will be used to generate the processor and bus clocks. The values allowed may depend on the FPGA or board you are using because certain on-chip resources (DCMs) may be required to perform clock division or multiplication.
Processor Clock Frequency: 300 MHz
Bus Clock Frequency: 100 MHz
JTAG Debug Interface: FPGA JTAG
On-Chip Memory (OCM) – Data: NONE
On-Chip Memory (OCM) – Instruction: NONE
Figure 1-8. Configure Processor Dialog Box
Select RS232_Uart_1 as the only external device. Select the 64-kb PLB controller and generate the linker script.
Click Next to display the Configure IO Interfaces dialog box. Check the RS232_Uart_1 option. Select OPB UARTLITE under Peripheral tab, 115200 under Baudrate tab and NONE under Parity, leaving the remaining devices with the default settings.
Refer to Figure 1-9. Note that the number of peripherals that appear on each window will depend on the resolution of your monitor.
Figure 1-9. Configure IO Interfaces Dialog Box
Uncheck the Ethernet_MAC option
Select <next>, un-checking all options, until you reach the Add Internal Peripherals dialog box
A PLB block RAM interface controller will be added by default. At this point you could click Add Peripheral to add additional internal peripherals, but you will see an alternative method in the next lab for adding internal peripherals to an existing project.
Figure 1-10. Add Internal Peripherals Dialog Box
Select 64 KB for the memory size and then click <Next> to display the Software Setup dialog box
Figure 1-11. Software Configuration Dialog Box
Click <Next> to view the memory test configuration options
Figure 1-12. Configure Memory Test Application
Click Next to display the System Created dialog box which summarizes the system being created. Note that the address map for the peripheral may differ.
Figure 1-13. System Created Dialog Box
Click Generate
A congratulations dialog box appears, indicating the files that BSB has created.
Click Finish to finish generating the project
Click <OK> to start using Platform Studio
Analyze the Created Project Step 2
Under the System tab, study the created project files and view the project in block diagram view.
Review the System Assembly window and observe the various components that are used in the design
Figure 1-14. System Assembly of the Generated Project
You will see the PowerPC processor, JTAG controller, plb2opb bridge, and plb_bram_if_cntlr connected to the PowerPC processor side. Notice that the opb_uartlite is connected to the opb bus.
1. Double-click the opb_uartlite block, go through the various fields, and complete the following:
Base address:
High address:
Explicit parameter value for C_BAUDRATE:
2. Why do you think that the DCM_module and proc_sys_reset instances do not have connections to any of the other blocks in the design?
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Notice that you can change the parameters (such as base address, address range, or C_BAUDRATE) here to reflect the design specifications.
Close the dialog box without saving any changes
The System Assembly viewer is useful for viewing the overall system and bus connectivity. For more detail, you will utilize other tools.
Generate the Hardware Netlists Step 3
Using PlatGen, generate the hardware netlist.
In XPS, select Hardware Generate Netlist or click 
in the toolbar
Observe the netlist generation in the output window as the generation progresses
Open Windows Explorer by selecting Start Programs Accessories Windows Explorer
Browse to the Lab1 project directory
Several directories containing VHDL wrappers and implementation netlists have been created.
3. List the directories that were created.
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Download the Test Application Step 4
In the Applications tab, right-click on TestApp_Peripheral software project and select “Mark to Initialize BRAM”.
Right-click on TestApp_Memory software project and unselect “Mark to initialize BRAMs”.
Select Device Configuration Update Bitstream
Note this will perform the following actions: run platform generator Generate the bitstream library generator compile the SW code merge the executable with the bitstream
Connect up the XUP board to power supply, download cable, and serial cable
Open hyperterminal and make the following settings
Select Device Configuration Download bitstream
You should see the following output
Conclusion
Base System Builder can be used in XPS to create a project. Several files—including an MHS file representing the processor system and a PBD file representing the schematic view—are created. After the system has been defined, the netlist of the processor system can be created. In a future lab, you will learn how to add other cores and simulate the design.
Answers
1. Double-click the top opb_uartlite block, go through the various fields, and complete the following:
Base address: 0x40600000
High address: 0x4060ffff
Explicit parameter value for C_BAUDRATE: 115200
2. Why do you think that the DCM_module and proc_sys_reset instances do not have connections to any of the other blocks in the design?
Both modules generate signals which are area connected to almost every module in the design. For example, the clock signal generated by DCM_module is connected to the processor, plb2opb bridge, and plb controller.
3. List the directories that were created.
• data (contains UCF file that stores pin location and timing constraints)
• etc (contains option file for controlling ISE tools and command file for controlling FPGA configuration)
• hdl (wrapper files for system, processor, and peripherals)
• implementation (netlist files for peripherals)
• pcores (repository for peripherals)
• ppc405_0 (software related files)
• synthesis (files resulting from synthesis)
• TestApp_Memory (software test application for memory)
• TestApp_Peripheral (software test application for peripherals)
• __xps (option files for various point tools in EDK)
Completed MHS File
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2 Build EDK_Im.14
# Tue Aug 29 14:15:28 2006
# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
# Family: virtex2p
# Device: xc2vp30
# Package: ff896
# Speed Grade: -7
# Processor: PPC 405
# Processor clock frequency: 300.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory : 64 KB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
BEGIN ppc405
PARAMETER INSTANCE = ppc405_0
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_0
BUS_INTERFACE IPLB = plb
BUS_INTERFACE DPLB = plb
PORT PLBCLK = sys_clk_s
PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
PORT RSTC405RESETCHIP = RSTC405RESETCHIP
PORT RSTC405RESETCORE = RSTC405RESETCORE
PORT RSTC405RESETSYS = RSTC405RESETSYS
PORT CPMC405CLOCK = proc_clk_s
END
BEGIN ppc405
PARAMETER INSTANCE = ppc405_1
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_1
END
BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_0
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = reset_block
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Ext_Reset_In = sys_rst_s
PORT Slowest_sync_clk = sys_clk_s
PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
PORT Core_Reset_Req = C405RSTCORERESETREQ
PORT System_Reset_Req = C405RSTSYSRESETREQ
PORT Rstc405resetchip = RSTC405RESETCHIP
PORT Rstc405resetcore = RSTC405RESETCORE
PORT Rstc405resetsys = RSTC405RESETSYS
PORT Bus_Struct_Reset = sys_bus_reset
PORT Dcm_locked = dcm_0_lock
END
BEGIN plb_v34
PARAMETER INSTANCE = plb
PARAMETER HW_VER = 1.02.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT PLB_Clk = sys_clk_s
END
BEGIN opb_v20
PARAMETER INSTANCE = opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT OPB_Clk = sys_clk_s
END
BEGIN plb2opb_bridge
PARAMETER INSTANCE = plb2opb
PARAMETER HW_VER = 1.01.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_NUM_ADDR_RNG = 1
PARAMETER C_RNG0_BASEADDR = 0x40600000
PARAMETER C_RNG0_HIGHADDR = 0x4060ffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE MOPB = opb
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = opb
PORT RX = fpga_0_RS232_Uart_1_RX
PORT TX = fpga_0_RS232_Uart_1_TX
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.b
PARAMETER c_plb_clk_period_ps = 10000
PARAMETER c_baseaddr = 0xffff0000
PARAMETER c_highaddr = 0xffffffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKFX_BUF = TRUE
PARAMETER C_CLKFX_DIVIDE = 1
PARAMETER C_CLKFX_MULTIPLY = 3
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DFS_FREQUENCY_MODE = HIGH
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFX = proc_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
