Lab 2- Adding IP to a Hardware Design
Targeting XUP Virtex-II Pro PowerPC
Adding IP to a Hardware Design Lab: PowerPC Processor
Introduction
This lab guides you through the process of adding additional IP to the existing processor system that you created in lab 1. You will learn two methods of adding additional IP: using the IP Catalog and modifying an MHS file with a text editor. At the end, you will modify the MHS file, create the design netlists, and implement the design and download the bitstream to the XUP Virtex-II Pro board.
Objectives
After completing this lab, you will be able to:
• Add additional IP to a hardware design
• Implement the design by utilizing Xflow
Procedure
The purpose of this lab exercise is to extend the hardware design started in Lab 1. Lab 1 included the PPC processor, PLB bus, JTAG_PPC, proc_Sys_Reset, DCM, PLB2OPB, an UART, PLB RAM controller, PLB BRAM, and OPB UART lite components. Lab 2 adds the remaining components, except for an MYIP instance for the LED, to extend the hardware design.
In this lab, you will use the dialog mode of the XPS system and text mode features to add the following IP to an existing processor system:
• PLB_BRAM_CNTLR for data
• BRAM for data
• OPB GPIO for Push button and Dip switches
You will also analyze the system.mhs file to understand the various sections of the hardware specifications of the microprocessor.
Figure 2-1. Additional IP
This lab comprises several steps, including adding IP to the processor system designed in Lab 1 and creating an ISE project used to implement the design. Below each general instruction for a given procedure, you will find accompanying step-by-step directions and illustrated figures providing more detail for performing the general instruction. If you feel confident about a specific instruction, feel free to skip the step-by-step directions and move on to the next general instruction in the procedure.
Open the Project Step 1
Create a lab2 folder and copy the contents of the lab1 folder into the lab2 folder if you wish to continue with the design you created in the previous lab. Launch Xilinx Platform Studio (XPS) and open the project file located in C:\xup\embedded\ppc\labs\lab2 (if you want to continue with your created design)
If you wish to continue using the design that you created in Lab 1, create a lab2 folder in the C:\xup\embedded\ppc\labs directory and copy the contents from lab1 to lab2
• Open XPS by selecting Start Programs Xilinx Platform Studio 8.2i Xilinx Platform Studio
• Select Open A Recent Project, Click OK and browse to C:\xup\embedded\ppc\labs\lab2
• Select system.xmp to open the project
Extend the Hardware System Step 2
Add the following IP to the processor system via the IP Catalog:
• PLB BRAM interface controller
• BRAM
• OPB_GPIO (two instances)
XPS provides two methods for adding peripherals to an existing project. You will use the first method, the IP Catalog, to add most of the additional IP and connect them. You will also use the second method, which is manually editing the MHS file.
Select the IP Catalog, which displays a list of all available IP for use in your system
Figure 2-2. Add/Edit Hardware Platform Specifications Dialog Box
Select each of the following peripherals and add it to the system by right-clicking on each peripheral and selecting Add IP :
• plb_bram_if_cntlr (1.00.b)
• bram_block (1.00.a)
• opb_gpio (3.01.b) – add two instances
Change the instance names of the peripherals which you just added to the names listed according to the table below.
At this point, the Peripherals tab should look like the following:
Figure 2-3. Peripherals Tab after Adding Peripherals
Set the bus connections as listed in the following table by expanding each peripheral and selecting the appropriate connection the Bus Connection Column
Table 2-1. Peripherals Bus Connections
Note: The dip_push device is slave device connected to the OPB bus. The plb_bram controller is a slave device connected to the PLB bus.
At this point, the Bus Connections should look like the following:
Figure 2-4. Assigning Bus Connections to the Added Peripherals
To connect the PORT A of the plb_bram_if_cntlr_2 memory controller to the PORT A of the BRAM memory, select the PORTA Bus Connection column under the plb_bram_if_cntlr_2_bram instance and select plb_bram_if_cntlr_2_PORTA
Figure 2-5. Specify connection between BlockRAM and Memory Controller
Rename the connector for port A of the plb_bram_if_cntlr_1 memory controller as plb_bram_if_cntlr_1_PORTA and assign it to port A of the plb_bram_if_cntrl_1_bram Block RAM.
Figure 2-6. Specify connection between BlockRAM and Memory Controller
Select the Addresses tab. You can manually assign the base and high addresses of your peripherals or have XPS do it. Enter the base address for the plb_bram_if_cntlr_2 instance and specify its size as listed in Table 2-2 below.
Note that after entering the base address and size, the high address is automatically calculated.
Table 2-2. Peripherals Memory Map
Enter the address size of 512 bytes for the dip and push instances
Lock down the addresses for plb_bram_if_cntrl_1 instance and the RS232_Uart_1 peripheral by clicking in the lock field adjacent to the base address.
For the rest of the addresses, let XPS create them by clicking Generate Addresses.
Notice that the OPB peripherals now reside in the address space for the PLB2OPB bridge
At this point, the Addresses tab should look like the following:
Figure 2-7. Addresses Tab after Changing the Added Peripheral Addresses
Select Project Generate and View Block Diagram to view the block diagram of the design built so far
Figure 2-8. Block Diagram View of the Design after Adding the Peripherals
Close the block diagram view
Configure the newly added peripherals.
Double-click on the dip instance and set the following parameters according to the figures below
Table 2-9. Common parameters for the dip instance
Figure 2-10. Channel 1 parameters for the dip instance
Double-click on the push instance and set the following parameters according to the figures below
Table 2-11. Common parameters for the push instance
Figure 2-12. Channel 1 parameters for the push instance
Add additional ports to peripherals and then connect them. These ports coincide with internal nets such as clock signals, as well as external FPGA pins that connect to board components including the push buttons and DIP switches.
Select the Ports filter in the System Assembly View
Expand dip1 and push1 to view the available ports
Change the connection signals by typing in the new values according to the table below.
Table 2-5. Additional Ports Added to Peripherals
After entering in the connections for the ports as described in the above step, select the Make External option from the drop down box for the same signals to make the connections external (connections to I/O pins on the FPGA).
In the External Ports Connections, make the changes to the port names, net names, polarity, and ranges as shown in the figure below. Delete any external pins that are tied to ground.
Figure 2-13. Ports tab after making dip_push GPIO as external
Add the code to implement the functionality of push button and dip switches
Click on Applications tab and double-click on TestApp_Memory.c file.
Table 2-14. Application tab containing the source code
Delete everything present inside the file and copy following code into the file.
Table 2-15. Snippet of source code.
Click on
to generate libraries, which will generate xparameters.h file in Applications tab under Processor.
Click on the system.ucf file under Project tab and add the following code to assign pins to push buttons and dip switches. Also update the IOSTANDARD for sys_rst_pin to LVCMOS25
Note: If there were any external ports tied to ground from the previous steps, delete the associated pin constraints.
Table 2-11. UCF file (pin assignments).
Click on
to compile the source code.
Analyze the MHS file Step 3
Open the system.mhs file, study its contents, and answer the following questions.
Double-click the system.mhs file to open it, if it is not already open
Study the external ports sections and answer the following questions
1. Complete the following
Number of external ports: 
Number of external ports that are output: 
Number of external ports that are bidirectional: 
Study the plb2opb instance section
2. Complete the following:
What is the value of the C_DCR_INTFCE: 
What does it signify? 
Name of the bus connected on the master side: 
Name of the bus connected on the slave side: 
Study the entire MHS file
3. List the instances to which the sys_clk_s is connected:
________________________________________________________________
________________________________________________________________
List the devices connected to the opb bus:
________________________________________________________________
________________________________________________________________
4. Draw the address map of the system, providing instance names. You can sort the peripheral addresses by base address from the Addresses section of the System Assembly view.
Download the Bitstream and Verify Operation Step 4
Configure and open a hyperterminal window. Generate the bitstream and download via EDK, and verify operation on the XUP Virtex-II Pro board.
Connect the board to the PC and turn it on.
Start the Hyperterminal on the PC and make its baud rate is set to 115200 and flow control is set to none and click on connect.
Click on
to download the program (bit file) on the board.
Note: If an error message appears indicating invalid ID code, Go to \lab2\etc folder and open download file in edit mode. Replace p 2 by p 3. Close the file and download again.
See the result on Hyperterminal as shown
Figure 2-17. Result on Hyperterminal.
Push the buttons and switches and notice the changing values in hyperterminal
Conclusion
Xilinx Platform Studio can create an MHS file representing the processor system. You can configure the system by using peripheral parameters and controlling internal and external ports. After defining the system, you can create the processor system netlists.
In future labs in this course, you will learn how to add user cores, add software to the system, simulate the design, debug the software, and verify the functionality of the completed design by using a hardware board.
Answers
1. Complete the following:
Number of external ports: 6
Number of external ports that are output: 1
Number of external ports that are input: 5
Number of external ports that are bidirectional: 0
2. Complete the following:
What is the value of the C_DCR_INTFCE: 0
What does it signify? DCR interface is not used
Name of the bus connected on the master side: opb
Name of the bus connected on the slave side: plb
3. List the instances to which the sys_clk_s is connected:
ppc405_0, reset_block, plb, opb, plb2opb, dcm_0, RS232_Uart_1, dip1, push1, plb_bram_if_cntlr_1, plb_bram_if_cntlr_2
List the devices connected to the opb bus:
plb2opb, RS232_Uart_1, dip, and push
4. Draw the address map of the system, providing instance names. You can sort the peripheral addresses by base address from the Addresses section of the System Assembly View.
Completed MHS File
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2 Build EDK_Im.14
# Tue Aug 29 14:15:28 2006
# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
# Family: virtex2p
# Device: xc2vp30
# Package: ff896
# Speed Grade: -7
# Processor: PPC 405
# Processor clock frequency: 300.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory : 64 KB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
PORT dip = DIP, DIR = I, VEC = [0:3]
PORT push = PUSH, DIR = I, VEC = [0:4]
BEGIN ppc405
PARAMETER INSTANCE = ppc405_0
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_0
BUS_INTERFACE IPLB = plb
BUS_INTERFACE DPLB = plb
PORT PLBCLK = sys_clk_s
PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
PORT RSTC405RESETCHIP = RSTC405RESETCHIP
PORT RSTC405RESETCORE = RSTC405RESETCORE
PORT RSTC405RESETSYS = RSTC405RESETSYS
PORT CPMC405CLOCK = proc_clk_s
END
BEGIN ppc405
PARAMETER INSTANCE = ppc405_1
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_1
END
BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_0
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = reset_block
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Ext_Reset_In = sys_rst_s
PORT Slowest_sync_clk = sys_clk_s
PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
PORT Core_Reset_Req = C405RSTCORERESETREQ
PORT System_Reset_Req = C405RSTSYSRESETREQ
PORT Rstc405resetchip = RSTC405RESETCHIP
PORT Rstc405resetcore = RSTC405RESETCORE
PORT Rstc405resetsys = RSTC405RESETSYS
PORT Bus_Struct_Reset = sys_bus_reset
PORT Dcm_locked = dcm_0_lock
END
BEGIN plb_v34
PARAMETER INSTANCE = plb
PARAMETER HW_VER = 1.02.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT PLB_Clk = sys_clk_s
END
BEGIN opb_v20
PARAMETER INSTANCE = opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT OPB_Clk = sys_clk_s
END
BEGIN plb2opb_bridge
PARAMETER INSTANCE = plb2opb
PARAMETER HW_VER = 1.01.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_RNG0_BASEADDR = 0x40000000
PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
PARAMETER C_NUM_ADDR_RNG = 1
BUS_INTERFACE SPLB = plb
BUS_INTERFACE MOPB = opb
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = opb
PORT RX = fpga_0_RS232_Uart_1_RX
PORT TX = fpga_0_RS232_Uart_1_TX
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.b
PARAMETER c_plb_clk_period_ps = 10000
PARAMETER c_baseaddr = 0xffff0000
PARAMETER c_highaddr = 0xffffffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_PORTA
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_PORTA
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKFX_BUF = TRUE
PARAMETER C_CLKFX_DIVIDE = 1
PARAMETER C_CLKFX_MULTIPLY = 3
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DFS_FREQUENCY_MODE = HIGH
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFX = proc_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_2
PARAMETER HW_VER = 1.00.b
PARAMETER c_baseaddr = 0x00000000
PARAMETER c_highaddr = 0x00003fff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_2_PORTA
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_2_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_2_PORTA
END
BEGIN opb_gpio
PARAMETER INSTANCE = dip1
PARAMETER HW_VER = 3.01.b
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x4002ffff
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
BUS_INTERFACE SOPB = opb
PORT GPIO_in = DIP
END
BEGIN opb_gpio
PARAMETER INSTANCE = push1
PARAMETER HW_VER = 3.01.b
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x4000ffff
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
BUS_INTERFACE SOPB = opb
PORT GPIO_in = PUSH
END
