Lab 3 - PowerPC Processor
Adding Custom IP to an Embedded System Lab:
Creating and Adding Custom IP to an Embedded System Lab: PowerPC Processor
Introduction
This lab guides you through the process of creating and adding a custom OPB peripheral the embedded system that you updated in lab 2. You will update the software code from lab 2 to write to this peripheral, and download and test on the XUP Virtex-II Pro board.
Objectives
After completing this lab, you will be able to:
• Create an IP using the Create/Import Peripheral Wizard
• Import the IP into EDK using the Create/Import Peripheral Wizard
• Add the custom IP to a real system
• Develop an application and generate a bitstream
• Download the bitstream and verify the functionality in actual hardware
Procedure
The purpose of this lab exercise is to complete the hardware design started in Lab 1 and extended in Lab 2. Lab 1 included the PPC, PLB bus, JTAG_PPC, proc_Sys_Reset, DCM, PLB2OPB, RS232_Uart_1, PLB RAM controller, and PLB BRAM components. Lab 2 added the remaining IP, except for an MYIP instance for the LED, to extend the hardware design.
In this lab, you will use the Create and Import Peripheral Wizard of Xilinx Platform Studio (XPS) to create a user peripheral from an HDL module, add an instance of the imported peripheral, and modify the system.ucf file to provide an interface to the on-board LED module.
Figure 3-1. Additional IP
This lab comprises several steps involving the creation of OPB custom IP (a simple 4-bit output to drive LEDs) and addition of a custom OPB peripheral. Although the change to the hardware is simple, this lab illustrates the integration of a user peripheral through the Create and Import Peripheral Wizard. This lab also illustrates the use of an existing peripheral to provide the OPB bus interface.
Below each general instruction for a given procedure, you will find accompanying step-by-step directions and illustrated figures providing more detail for performing the general instruction. If you feel confident about a specific instruction, feel free to skip the step-by-step directions and move on to the next general instruction in the procedure.
Creating a Custom IP Step 1
Create a lab3 folder and copy the contents of the lab2 folder into the lab3 folder if you wish to continue with the design you created in the previous lab. Launch the Create – Import Peripheral wizard. Name the peripheral as my_led and let it be for OPB bus.
If you wish to continue using the design that you created in Lab 2, create a lab3 folder in the C:\xup\embedded\ppc\labs directory and copy the contents from lab2 to lab3
Invoke the Create/Import Peripheral Wizard via Start Programs Xilinx Platform Studio 8.2i Accessories Create or Import Peripheral Wizard
Click Next to continue
In the Select Flow panel, select Create templates for a new peripheral and click Next
In the Repository or Project panel, select To an XPS Project and click Next
Figure 3-2. Repository or Project Dialog Box
In the Name and Version panel, enter my_led as the peripheral name, accept default versions, and click Next
Figure 3-3. Name and Version Dialog Box
In the Bus Interfaces panel, select On-chip Peripheral Bus (OPB), and click Next
Figure 3-4. Bus Interface Dialog Box
Continuing with the wizard, select RST/MIR and User Logic S/W Register support. Select only one software accessible register of 32-bit width. Generate template driver files. Browse to the C:\xup\embedded\ppc\labs\lab3 directory and answer the questions at the end of this step
In the IPIF Services panel, select S/W Reset and MIR and User Logic S/W Register Support
Figure 3-5. IPIF Services Dialog Box
Click Next
In the User S/W Register panel, select the second option (Disable posted write behavior for normal acknowledged write behavior) and click next leaving the other options default
Figure 3-6. User S/W Register Dialog Box
Scroll through the IP Interconnect (IPIC) panel, which displays the default IPIC signal which are available for the user logic based on the previous selection, click Next
Figure 3-7. IP Interconnect (IPIC) Dialog Box
In the (OPTIONAL) Peripheral Simulation Support panel, uncheck Generate BFM simulation platform in order not to generate the BFM simulation associated files and directories, and click Next
Figure 3-8. Peripheral Simulation Support Dialog Box
In the (OPTIONAL) Peripheral Implementation Options panel, uncheck Generate ISE and XST project files to help you to implement the peripheral using XST flow and check Generate template driver files to help you to implement software interface
Figure 3-9. Peripheral Implementation Options Dialog Box
Click Next, and you will see the summary information panel
Figure 3-10. Congratulations Dialog Box
Click Finish to close the wizard
Add LED port in my_led_v2_1_0.mpd file generated by the wizard in C:\xup\embedded\ppc\labs\lab3\pcores\my_led_v1_00_a\data directory
Using Windows Explorer, browse to C:\xup\embedded\ppc\labs\lab3\pcores\my_led_v1_00_a\data directory
Open my_led_v2_1_0.mpd file using a text editor
Add the following line before the OPB_Clk port under the Ports section PORT LED = “ “, DIR = O, VEC = [0:3] .This is necessary for the port to appear in IP Catalog
Save the file and close
Open the my_led.vhd and user_logic.vhd files in the Text Editor window from C:\XUP\embedded\ppc\labs\lab3\pcores\my_led_v1_00_a\hdl\vhdl directory. Add necessary declarations and logic in my_led.vhd and user_logic.vhd files.
Browse to C:\xup\embedded\labs\lab3\pcores\my_led_v1_00_a\hdl\vhdl directory.
Right click on my_led.vhd file and open it with text editor program.
Add user port LED under USER ports added here token
Figure 3-11. Add the User Port LED
Search for next --USER and add port mapping statement
Figure 3-12. Add Port Mapping Statement
Open user_logic.vhd file from \vhdl directory and add LED port definition in the USER Ports area
Figure 3-13. Add the LED Port Definition
Search for next --USER and add the internal signal declaration for the user logic
Figure 3-14. Internal Signal Declaration for the User Logic
Search for –USER logic implementation and add the following code
Figure 3-15. Add Code
Save changes and close
Importing and Adding Custom IP to the Project Step 2
Using the IP Catalog from XPS, add my_led to the project, make bus connections, generate address for the my_led instance, add necessary ports to the instance, name them appropriately and bring out the data port. Add following to the UCF file:
Net led<0> LOC=AC4;
Net led<1> LOC=AC3;
Net led<2> LOC=AA6;
Net led<3> LOC=AA5;
Open the lab 3 project in XPS
In the IP Catalog tab, expand Project Repository and add the custom peripheral my_led to the hardware system
Figure 3-21. User Created Peripheral in IP Catalog
Switch to the Bus Connections section, attach my_led_0 to the OPB bus as illustrated in figure 3-22
Figure 3-21. Connect User Created Peripheral to OPB Bus
Select the Addresses filter and lock down the addresses of all peripherals accept for my_led_0
Select size as 512 from drop down box for my_led_0 and click Generate Addresses
Switch to the Ports section and perform the following
• Locate my_led_0’s LED port in the table, modify its Net Name to fpga_0_LEDs_4Bit_GPIO_d_out by typing in the Net field
• Click Make External to make the above net external and rename the external pins to led
Figure 3-22. Connect User Created Peripheral Ports to External FPGA pins
Open up the system.mhs file and verify following snippets
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
PORT dip = DIP, DIR = I, VEC = [0:3]
PORT push = PUSH, DIR = I, VEC = [0:4]
PORT led = fpga_0_LEDs_4Bit_GPIO_d_out, DIR = O, VEC = [0:3]
Add following pin assignments in the UCF file
Net led<0> LOC=AC4;
Net led<1> LOC=AC3;
Net led<2> LOC=AA6;
Net led<3> LOC=AA5;
Save and close the UCF file
Generate and download bitstream Step 3
Generate and download the bitstream. Verify that the design operates as did in the previous lab. You will modify the software in the next lab to write to the LEDs.
Click Device Configuration Update Bitstream to generate the bit file
Download the bit file on the board
Change dip switch settings and push the buttons, verifying output on hyperterminal
Conclusion
This lab led you through the process of creating a custom IP and adding it to the embedded system
Completed MHS File
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2 Build EDK_Im.14
# Tue Aug 29 14:15:28 2006
# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
# Family: virtex2p
# Device: xc2vp30
# Package: ff896
# Speed Grade: -7
# Processor: PPC 405
# Processor clock frequency: 300.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory : 64 KB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
PORT dip = DIP, DIR = I, VEC = [0:3]
PORT push = PUSH, DIR = I, VEC = [0:4]
PORT led = fpga_0_LEDs_4Bit_GPIO_d_out, DIR = O, VEC = [0:3]
BEGIN ppc405
PARAMETER INSTANCE = ppc405_0
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_0
BUS_INTERFACE IPLB = plb
BUS_INTERFACE DPLB = plb
PORT PLBCLK = sys_clk_s
PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
PORT RSTC405RESETCHIP = RSTC405RESETCHIP
PORT RSTC405RESETCORE = RSTC405RESETCORE
PORT RSTC405RESETSYS = RSTC405RESETSYS
PORT CPMC405CLOCK = proc_clk_s
END
BEGIN ppc405
PARAMETER INSTANCE = ppc405_1
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_1
END
BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_0
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = reset_block
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Ext_Reset_In = sys_rst_s
PORT Slowest_sync_clk = sys_clk_s
PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
PORT Core_Reset_Req = C405RSTCORERESETREQ
PORT System_Reset_Req = C405RSTSYSRESETREQ
PORT Rstc405resetchip = RSTC405RESETCHIP
PORT Rstc405resetcore = RSTC405RESETCORE
PORT Rstc405resetsys = RSTC405RESETSYS
PORT Bus_Struct_Reset = sys_bus_reset
PORT Dcm_locked = dcm_0_lock
END
BEGIN plb_v34
PARAMETER INSTANCE = plb
PARAMETER HW_VER = 1.02.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT PLB_Clk = sys_clk_s
END
BEGIN opb_v20
PARAMETER INSTANCE = opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT OPB_Clk = sys_clk_s
END
BEGIN plb2opb_bridge
PARAMETER INSTANCE = plb2opb
PARAMETER HW_VER = 1.01.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_RNG0_BASEADDR = 0x40000000
PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
PARAMETER C_NUM_ADDR_RNG = 1
BUS_INTERFACE SPLB = plb
BUS_INTERFACE MOPB = opb
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = opb
PORT RX = fpga_0_RS232_Uart_1_RX
PORT TX = fpga_0_RS232_Uart_1_TX
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.b
PARAMETER c_plb_clk_period_ps = 10000
PARAMETER c_baseaddr = 0xffff0000
PARAMETER c_highaddr = 0xffffffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_PORTA
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_PORTA
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKFX_BUF = TRUE
PARAMETER C_CLKFX_DIVIDE = 1
PARAMETER C_CLKFX_MULTIPLY = 3
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DFS_FREQUENCY_MODE = HIGH
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFX = proc_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_2
PARAMETER HW_VER = 1.00.b
PARAMETER c_baseaddr = 0x00000000
PARAMETER c_highaddr = 0x00003fff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_2_PORTA
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_2_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_2_PORTA
END
BEGIN opb_gpio
PARAMETER INSTANCE = dip1
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x400201ff
BUS_INTERFACE SOPB = opb
PORT GPIO_in = DIP
END
BEGIN opb_gpio
PARAMETER INSTANCE = push1
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x400001ff
BUS_INTERFACE SOPB = opb
PORT GPIO_in = PUSH
END
BEGIN my_led
PARAMETER INSTANCE = my_led_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x7D800000
PARAMETER C_HIGHADDR = 0x7D8001FF
BUS_INTERFACE SOPB = opb
PORT LED = fpga_0_LEDs_4Bit_GPIO_d_out
END
