69． 用modelsim后仿真时需要用到XILINX的库, 下载了XILINX网址提供的TCL文件, 按照要求在AUTOEXEC. BAT中设置了SET MODELSIM=****, 重启了机器, 在MODELSIM下运行了TCL文件, 选项为VERILOG, simprim, 可是MODELSIM 还是报找不到库, 为什么？所用ISE版本为ISE4. 1I.
答：The tcl script is for compiling the Xilinx libraries with Modelsim. After you've compile the libraries, you need to vmap them when you simulate your design. For example, if the physical path to your compiled simprim library is d:/xilinx_sim_model/simprim, you need to map simprim to the full path by typing "vmap simprim d:/xilinx_sim_model/simprim" at the Modelsim command prompt. Then you can simulate your design by the following command "vsim -L simprim " （参考译文件：tcl脚本是为使用Modelsim编译Xilinx库的. 在编译完库之后, 仿真设计时需要vmap这些库. 例如, 如果指向已编译的simprim库的物理路径是d:/xilinx_sim_model/simprim, 则需要通过在Modelsim命令提示处输入"vmap simprim d:/xilinx_sim_model/simprim"来将simprim映射到完整路径. 然后可以使用命令"vsim -L simprim "仿真设计. ）
70． PIN HSWAP＿EN的作用是使能或关闭配置时I/O管脚上的上拉电阻, 这两种情况具体有什么不同呢？PCB设计时HSWAP＿EN具体如何处理？
答：The Virtex-II HSWAP-EN pin has an internal pull-up by default to turn off the pull-up resistors at the I/O pins during configuration. You need to tie it low externally if you need to activate the pull-up at I/O pins during configuration. （参考译文：缺省情况下, Virtex-II HSWAP-EN管脚有一个内部上拉电阻, 以在配置期间关闭I/O管脚上的上拉电阻. 如果在配置过程中需要激活I/O管脚的上拉电阻, 需要将这个上拉电阻在表面上约束到较低. ）
71． PWRDWN＿B是power down pin, 可不可以不连接或上拉？
答：The PWRDWN_B pin was provided to set a Virtex-II device into a power-down mode: a low-power, inactive state. However, this feature is no longer supported in Virtex-II. To set it as inactive, the PWRDWN_B should be left at its default value, which is pulled up. (The PWRDWN_B does not require an external pull-up or pull-down. ). Please refer to Xilinx website for more details. （参考译文：PWRDWN_B管脚用于将Virtex-II器件设定为功率下降模式：低功率和不活动状态. 然而Virtex-II中已不再支持这种功能. 要在非活动状态下设定它, PWRDWN_B应该保留缺省值, 即已上拉. PWRDWN_B不要求外部上拉或下拉. 详情讲参阅Xilinx网站）.
72． spartanII不能下载, 显示done不能拉高, done上上拉电阻已接, 是何原因？
答： Here are my suggestions（有几点建议：）
-Check if the mode pin is selected correctly. （检查是否正确选择了方式管脚）.
- Check if you have selected the correct startup clock. If you are using serial mode, you need to use Cclk. If you are using jtag, you
