串行数据接收机测试加入模拟信号的数字模式
Designers who work with serial buses and systems know that critical specifications,especially data rates, are constantly advancing. Higher speeds mean shrinking operating margins. These in turn contribute to diminishing tolerances that complicate the pursuit of flawless interoperability among system elements. Measurements –in the lab, during compliance testing, and in production – play a major role in
promoting interoperability. Testing has become the focus of industry- wide attention as designers strive to develop technologies and measurement procedures that maximize both performance and interoperability.
Losses, Aberrations Pursue Serial Signals The common serial data receiver, an element used by the hundreds in digital systems of all kinds, poses one of the biggest challenges for designers who need to exercise and characterize emerging devices. As usual,the fundamental questions are “Will the receiver work in real world conditions?” and “What is its worst-case behavior?” In actuality, the typical serial data receiver often operates in a real world that essentially is the worst case.
Why? Because signals traversing a given transmission link tend to degrade in proportion to their clock rate and the length of the transmission path. Even the most carefully controlled link has more impact on, for example, a 6.0 Gb/s signal than a 500 Mb/s signal. Next-generation serial standards will see data rates escalate to 6.0 Gb/s and beyond, with no end in sight. Serial data signals are demanding more and more of the circuit elements that deliver them.
Equally important, real-world applications often stray from the ideal of a controlled-impedance signal path with minimal length and minimal disruptions. Practical manufacturing economies dictate the use of relatively lossy media such as FR4 epoxy circuit boards.
Packaging requirements rather than electrical considerations drive circuit layouts. And mass-produced cables and connectors routinely trade off signal fidelity in favor of cost-effective simplicity. System designers knowingly balance transmission path integrity against
the realities of cost and competition.
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promoting interoperability. Testing has become the focus of industry- wide attention as designers strive to develop technologies and measurement procedures that maximize both performance and interoperability.
Losses, Aberrations Pursue Serial Signals The common serial data receiver, an element used by the hundreds in digital systems of all kinds, poses one of the biggest challenges for designers who need to exercise and characterize emerging devices. As usual,the fundamental questions are “Will the receiver work in real world conditions?” and “What is its worst-case behavior?” In actuality, the typical serial data receiver often operates in a real world that essentially is the worst case.
Why? Because signals traversing a given transmission link tend to degrade in proportion to their clock rate and the length of the transmission path. Even the most carefully controlled link has more impact on, for example, a 6.0 Gb/s signal than a 500 Mb/s signal. Next-generation serial standards will see data rates escalate to 6.0 Gb/s and beyond, with no end in sight. Serial data signals are demanding more and more of the circuit elements that deliver them.
Equally important, real-world applications often stray from the ideal of a controlled-impedance signal path with minimal length and minimal disruptions. Practical manufacturing economies dictate the use of relatively lossy media such as FR4 epoxy circuit boards.
Packaging requirements rather than electrical considerations drive circuit layouts. And mass-produced cables and connectors routinely trade off signal fidelity in favor of cost-effective simplicity. System designers knowingly balance transmission path integrity against
the realities of cost and competition.
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