IC verification engineer(beijing) Job Description: In this key role, you will be instrumental in the development of infrastructure for the validation of architectures and the
verification of hardware. Additional duties include the development
of directed and random hardware verification environments, and the
application of those environments to SOC verification; debugging C
simulation models, RTL simulations and hardware emulation.
Candidate Qualifications: - Extensive Verilog experience with
SOC verification environments. (Experience with VCS a plus.) - Communications, ARM, AXI, Ethernet,
USB, Video processing, acceleration background - Experience developing bus
functional models, monitors, scoreboards, generators, functional
coverage models - Experience in using reference
models to verify hardware - Shell scripts and Perl expertise,
create runsim, lsf, regression management scripts - Experience with high level
verification languages such as SystemC, SystemVerilog, OVM, VMM,
Vera or Specman, as well as System C/ C / C++ programming
background - Able to understand verilog RTL
code, debug simulation errors, identify and fix RTL/Environment
issues - Excellent communication skills as
detailed documentation of test plans and test matrixes - Team player, and easy to work with
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