ASIC Verification Engineer

LSI上海研发中心高薪诚聘通讯存储领域人才，薪水待遇优厚，今年开始配股了，部分人员有出国培训机会。(部门内部推荐,成功机会更大)

有意者请将中英文简历发送至：asic_tapeout@hotmail.com

ASIC Verification Engineer

DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
As a member of the Read Channel team, candidate must be willing to work as an extended
member of the design team. Duties will include functional verification of Storage read
channel mixed-signal IP. Candidate will be expected to contribute to design and development
of System Verilog based verification environment and will be responsible for verification
closure of block/chip/system level functions for mixed signal based IP. Experience with
System Verilog and functional coverage methodologies are required. Must be willing to
follow a disciplined verification methodology and to work closely with a multi-location,
international design team. Excellent teamwork and communication skills are required.
PREFERRED EXPERIENCE:
BSEE with 3-5+ years of design and/or verification experience required, MSEE preferred.
Required knowledge and skills:
- Expertise in System Verilog required
- Good understanding of Digital Signal Processing
- Good understanding of Analog and Digital Circuits
- Very good analytical/debugging skill
- Good verbal and written communication skills
Desirable skills:
- Knowledge of Verilog-AMS, Perl
- Knowledge of verification methodologies including functional coverage and constrained
random testing
- Knowledge of VLSI design flows & DFT
- Familiarity of high level programming language
- Experience working with globally distributed team