看了这篇文章, 没有SG也没问题了

对于很多应用如果我们能自己编写代码, 就可以进行有针对性地算法优化, 个人也会很有成就感.

这篇文章从编码的角度为我们提供了很多有价值的信息, 在前面数制编码的基础上仔细体会相信会让版上各位兄弟对DSP ON FPGA有更多更深入的理解.

看看！！！

有兴趣的读者可以简单看看summary， introduction 和 conclusion 

Summary:

This application note provides design advice for implementing arithmetic logic functions in two High-Level Design Languages (HDLs), VHDL and Verilog.

 

Introduction

This application note discusses design considerations for HDL coding of simple arithmetic
functions in Virtex™ devices. HDL code examples for implementing adders, subtracters, two's
complementers, comparators and multipliers are provided in the reference design. Because it
is without primitive instantiations, the HDL code is portable across the Virtex device families.

 

The focus on arithmetic functions is due to their common usage in Digital Signal Processing
(DSP) based designs. DSP is increasingly being used in wireless applications and involve a
large number of repetitive arithmetic operations. For the best, high-performance utilization of
the FPGA, the fewest logic cells with a minimum delay must be used by these arithmetic
operations. The Virtex series employs a powerful Configurable Logic Block (CLB) architecture
with the requisite speed, utilization and re-programmability advantages. The Virtex architecture
combined with HDL coding guidelines help to achieve the target performance.

 

Conclusion

HDL coding style can greatly affect the way arithmetic logic is synthesized. Dealing with signed
and unsigned numbers and operands with different bits are important considerations when
coding arithmetic operations. The Virtex architecture is very efficient for implementing
arithmetic operations using features of the CLB such as the carry logic and the dedicated AND
gate. In DSP applications, fast and efficient implementation of elementary arithmetic function
blocks becomes especially important. A good example is the Multiply and Accumulate (MAC)
operation used repeatedly, in very large numbers, in DSP building blocks.

In addition to coding style, the role of the synthesis tool in leveraging the features of the Virtex
architecture is significant. Synthesis tools are observed to infer fast and dense logic for the
most part by operator inference. Designers using an HDL flow need to be aware of the
capabilities of their synthesis tool and the target device architecture.

 

深感英文太差,中文资料太少!
英语学不好的人,不要搞it了.

没办法啊, 这个世界是平的, 如果你看到那些老外费着牛劲学汉语的样子体会会更深

thank you

看来是就当学习英语了。。。。

很好，从算法本身入手才是硬道理！

good stuff,thanks