请教串行变并行模块的问题兼读程序的问题

----开发板上的程序,说是串行变并行模块，但是看不懂是怎么实现的，几个进程越看越糊涂
想问下看懂的高手，遇到这种情况，或者说看别人程序时有无技巧；哪位高手高抬贵手把关键语句注解一下，感激不尽

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rs232 is
port(sysclk: in std_logic;----系统时钟
rxd: in std_logic;---串行入口口------
disp: out std_logic_vector(7 downto 0)-------数据输出
);
end rs232;
architecture behv of rs232 is
signal b: std_logic_vector(9 downto 0);
signal r: std_logic_vector(3 downto 0);
signal j: std_logic_vector(7 downto 0);
signal frxd,gt,gtclr,cclk,gate: std_logic;
begin
1 gate<=gt and cclk;
2 disp(7 downto 0)<='0'&b(7 downto 1);
3 frxd<=not rxd;
4 s1:process(sysclk,gt)
4 begin
5 if gt='0' then j<=(others=>'0');
6 elsif sysclk'event and sysclk ='1' then
7 if j="1101000" then j<=(others=>'0');
8 else j<=j+1;
9 end if;
10 end if;
11 end process;
12 s2:process(j)
13 begin
14 if j="111001" then cclk<='1';
15 else cclk<='0';
16 end if;
17 end process;
18 s3:process(gate,gtclr)
19 begin
20 if gtclr='1' then r<="0000";
21 elsif gate'event and gate='1' then
22 r<=r+1;
23 end if;
24 end process;
2526 s4:process(gate,r)
27 begin
28 if r="1010" then gtclr<=not gate;
29 else gtclr<='0';
30 end if;
31 end process;
32 s5:process(gate,rxd,b)
33 begin
34 if gate'event and gate='1' then
35 b(9 downto 0)<=rxd&b(9 downto 1);
36 end if;
37 end process;
38 s6:process(frxd,gtclr)
39 begin
40 if gtclr='1' then gt<='0';
41 elsif frxd'event and frxd='1' then
42 gt<='1';
43 end if;
44 end process;
end behv;

不懂！

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rs232 is
port(sysclk: in std_logic;----系统时钟
rxd: in std_logic;---串行入口口------
disp: out std_logic_vector(7 downto 0)-------数据输出
);
end rs232;
首先看端口定义，分析输入输出的关系，由上面可知并行输出是8位的
architecture behv of rs232 is
signal b: std_logic_vector(9 downto 0);
signal r: std_logic_vector(3 downto 0);
signal j: std_logic_vector(7 downto 0);
signal frxd,gt,gtclr,cclk,gate: std_logic;
再看信号定义，编这个程序的人不够职业:)
begin
1 gate<=gt and cclk;
2 disp(7 downto 0)<='0'&b(7 downto 1);
3 frxd<=not rxd;
这部分是组合电路，下面是时序部分
计数器：104
4 s1:process(sysclk,gt)
4 begin
5 if gt='0' then j<=(others=>'0');
6 elsif sysclk'event and sysclk ='1' then
7 if j="1101000" then j<=(others=>'0');
8 else j<=j+1;
9 end if;
10 end if;
11 end process;
这部分是组合电路
计数器：57时，cclk<='1';
12 s2:process(j)
13 begin
14 if j="111001" then cclk<='1';
15 else cclk<='0';
16 end if;
17 end process;
非常不好的coding style，门控时钟
18 s3:process(gate,gtclr)
19 begin
20 if gtclr='1' then r<="0000";
21 elsif gate'event and gate='1' then
22 r<=r+1;
23 end if;
24 end process;
2526 s4:process(gate,r)
27 begin
28 if r="1010" then gtclr<=not gate;
29 else gtclr<='0';
30 end if;
31 end process;
移位寄存
32 s5:process(gate,rxd,b)
33 begin
34 if gate'event and gate='1' then
35 b(9 downto 0)<=rxd&b(9 downto 1);
36 end if;
37 end process;
糟糕透了
38 s6:process(frxd,gtclr)
39 begin
40 if gtclr='1' then gt<='0';
41 elsif frxd'event and frxd='1' then
42 gt<='1';
43 end if;
44 end process;
end behv;
结论：此代码不读也罢

受教了！