请教高手

      我在运用SDK编写应用软件程序时涉及到对浮点数的运算,而我的硬件平台一般是使用系统默认的设置,结果往往是导致应用软件编译不通过,说是内存地址不匹配.我想请问在处理浮点数时是否要注意哪些方面?如何才能控制地址的扩散?好象在SDK上编程和在VC上编程有比较大的不同.还望高手指点.....

嗨没有来得及回复你邮件，
以后都来这里吧，呵呵
你的问题，看上去像空间不足，改为DDR之外，也要增加heap& stack试试看。

能不能把你的MHS、MSS、出错部分的C code和Error信息发上来看看？另外你一定要用浮点运算吗？如果精度要求不是太高，建议做一下定点化处理。如果一定需要浮点运算，建议用高版本的EDK，MB7以上的FPU效率比较高。

把所有的编译文件都放进DDR SDRAM中吧，而不只是boot memory
你这个程序编译出来的会蛮大的。
你要是愿意，可以把
MHS、MSS、出错部分的C code和Error
都放上来，让大家都看一下：）

浮点运算需要用到的库比较大，你的BRAM不够大。
让Link Script指定所有段都放到ddr上试试看。

很不错啊
！！！！！！！！！

该给分了！！！！！！！！！！！！

首先非常感谢各位高手的指点,我的MHS和MSS文件:
PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX, DIR = I
PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_d_out_pin = fpga_0_LEDs_8Bit_GPIO_d_out, DIR = O, VEC = [0:7]
PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin = fpga_0_DIP_Switches_4Bit_GPIO_in, DIR = I, VEC = [0:3]
PORT fpga_0_Buttons_4Bit_GPIO_in_pin = fpga_0_Buttons_4Bit_GPIO_in, DIR = I, VEC = [0:3]
PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN, DIR = O
PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN, DIR = O, VEC = [0:0]
PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN, DIR = O
PORT fpga_0_FLASH_emc_ben_gnd_pin = net_gnd, DIR = O
PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A, DIR = O, VEC = [8:31]
PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ, DIR = IO, VEC = [0:7]
PORT fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O, DIR = IO
PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]
PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [1:0]
PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [1:0]
PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [15:0]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST

BEGIN microblaze
PARAMETER HW_VER = 7.00.a
PARAMETER INSTANCE = microblaze_0
PARAMETER C_INTERCONNECT = 1
PARAMETER C_USE_FPU = 1
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 2048
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 2048
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_ICACHE_BASEADDR = 0x86000000
PARAMETER C_ICACHE_HIGHADDR = 0x87ffffff
PARAMETER C_DCACHE_BASEADDR = 0x86000000
PARAMETER C_DCACHE_HIGHADDR = 0x87ffffff
PARAMETER C_AREA_OPTIMIZED = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE ixcl = ixcl
BUS_INTERFACE dxcl = dxcl
BUS_INTERFACE DEBUG = microblaze_0_dbg
PORT RESET = mb_reset
PORT Interrupt = Interrupt
END
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.00.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_DCE
PARAMETER HW_VER = 1.00.a
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_DCE_RX
PORT TX = fpga_0_RS232_DCE_TX
PORT Interrupt = RS232_DCE_Interrupt
END
BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERRUPT_PRESENT = 1
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_d_out = fpga_0_LEDs_8Bit_GPIO_d_out
PORT IP2INTC_Irpt = LEDs_8Bit_IP2INTC_Irpt
END
BEGIN xps_gpio
PARAMETER INSTANCE = DIP_Switches_4Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERRUPT_PRESENT = 1
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x81420000
PARAMETER C_HIGHADDR = 0x8142ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_in = fpga_0_DIP_Switches_4Bit_GPIO_in
PORT IP2INTC_Irpt = DIP_Switches_4Bit_IP2INTC_Irpt
END
BEGIN xps_gpio
PARAMETER INSTANCE = Buttons_4Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_INTERRUPT_PRESENT = 1
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_DUAL = 0
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x81440000
PARAMETER C_HIGHADDR = 0x8144ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_in = fpga_0_Buttons_4Bit_GPIO_in
PORT IP2INTC_Irpt = Buttons_4Bit_IP2INTC_Irpt
END
BEGIN xps_mch_emc
PARAMETER INSTANCE = FLASH
PARAMETER HW_VER = 1.00.a
PARAMETER C_NUM_CHANNELS = 0
PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_MAX_MEM_WIDTH = 8
PARAMETER C_MEM0_WIDTH = 8
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
PARAMETER C_SYNCH_MEM_0 = 0
PARAMETER C_TCEDV_PS_MEM_0 = 110000
PARAMETER C_TWC_PS_MEM_0 = 110000
PARAMETER C_TAVDV_PS_MEM_0 = 110000
PARAMETER C_TWP_PS_MEM_0 = 70000
PARAMETER C_THZCE_PS_MEM_0 = 35000
PARAMETER C_TLZWE_PS_MEM_0 = 15000
PARAMETER C_MEM0_BASEADDR = 0x85000000
PARAMETER C_MEM0_HIGHADDR = 0x85ffffff
BUS_INTERFACE SPLB = mb_plb
PORT Mem_A = fpga_0_FLASH_Mem_A_split
PORT Mem_DQ = fpga_0_FLASH_Mem_DQ
PORT Mem_OEN = fpga_0_FLASH_Mem_OEN
PORT Mem_WEN = fpga_0_FLASH_Mem_WEN
PORT Mem_CEN = fpga_0_FLASH_Mem_CEN
END
BEGIN mpmc
PARAMETER INSTANCE = DDR_SDRAM
PARAMETER HW_VER = 3.00.a
PARAMETER C_NUM_PORTS = 3
PARAMETER C_PIM0_BASETYPE = 1
PARAMETER C_PIM1_BASETYPE = 1
PARAMETER C_MEM_PARTNO = MT46V16M16-6
PARAMETER C_SPECIAL_BOARD = S3E_STKIT
PARAMETER C_MEM_BANKADDR_WIDTH = 2
PARAMETER C_MEM_DATA_WIDTH = 16
PARAMETER C_MEM_DQS_WIDTH = 2
PARAMETER C_MEM_DM_WIDTH = 2
PARAMETER C_MEM_TYPE = DDR
PARAMETER C_XCL0_WRITEXFER = 0
PARAMETER C_PIM2_BASETYPE = 2
PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
PARAMETER C_MPMC_BASEADDR = 0x86000000
PARAMETER C_MPMC_HIGHADDR = 0x87ffffff
PARAMETER C_SPLB2_NATIVE_DWIDTH = 32
BUS_INTERFACE XCL0 = ixcl
BUS_INTERFACE XCL1 = dxcl
BUS_INTERFACE SPLB2 = mb_plb
PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
PORT MPMC_Clk0 = DDR_SDRAM_mpmc_clk_s
PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
PORT MPMC_Rst = sys_bus_reset
END
BEGIN xps_bram_if_cntlr
PARAMETER INSTANCE = xps_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_SPLB_NATIVE_DWIDTH = 32
PARAMETER C_BASEADDR = 0x84a08000
PARAMETER C_HIGHADDR = 0x84a09fff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
BEGIN bram_block
PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END
BEGIN xps_timer
PARAMETER INSTANCE = xps_timer_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
BUS_INTERFACE SPLB = mb_plb
PORT Interrupt = xps_timer_1_Interrupt
END
BEGIN util_bus_split
PARAMETER INSTANCE = FLASH_util_bus_split_3
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 32
PARAMETER C_LEFT_POS = 0
PARAMETER C_SPLIT = 8
PORT Sig = fpga_0_FLASH_Mem_A_split
PORT Out2 = fpga_0_FLASH_Mem_A
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 50000000
PARAMETER C_CLKOUT0_FREQ = 50000000
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT1_FREQ = 100000000
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = GROUP0
PARAMETER C_CLKOUT2_FREQ = 100000000
PARAMETER C_CLKOUT2_PHASE = 90
PARAMETER C_CLKOUT2_GROUP = GROUP0
PORT CLKOUT0 = sys_clk_s
PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_s
PORT CLKOUT2 = DDR_SDRAM_mpmc_clk_90_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
END
BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 1.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
END
BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x81800000
PARAMETER C_HIGHADDR = 0x8180ffff
BUS_INTERFACE SPLB = mb_plb
PORT Irq = Interrupt
PORT Intr = RS232_DCE_Interrupt & LEDs_8Bit_IP2INTC_Irpt & DIP_Switches_4Bit_IP2INTC_Irpt & Buttons_4Bit_IP2INTC_Irpt & xps_timer_1_Interrupt
END
MSS:
PARAMETER VERSION = 2.2.0

BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 1.00.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER STDIN = RS232_DCE
PARAMETER STDOUT = RS232_DCE
END

BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.11.a
PARAMETER HW_INSTANCE = microblaze_0
PARAMETER COMPILER = mb-gcc
PARAMETER ARCHIVER = mb-ar
END

BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = lmb_bram
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.12.a
PARAMETER HW_INSTANCE = RS232_DCE
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.11.a
PARAMETER HW_INSTANCE = LEDs_8Bit
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.11.a
PARAMETER HW_INSTANCE = DIP_Switches_4Bit
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 2.11.a
PARAMETER HW_INSTANCE = Buttons_4Bit
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = emc
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = FLASH
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = mpmc
PARAMETER DRIVER_VER = 1.01.a
PARAMETER HW_INSTANCE = DDR_SDRAM
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = xps_bram_if_cntlr_1_bram
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = tmrctr
PARAMETER DRIVER_VER = 1.10.b
PARAMETER HW_INSTANCE = xps_timer_1
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = FLASH_util_bus_split_3
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = clock_generator_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 1.12.a
PARAMETER HW_INSTANCE = debug_module
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = proc_sys_reset_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = intc
PARAMETER DRIVER_VER = 1.10.c
PARAMETER HW_INSTANCE = xps_intc_0
END
程序简单的测试浮点数:
int main()
{
int m;
double i=3.1415,j=5.4321,k;
for(m=0;m<60;m++)
{
j=j+i;
k=i*j;
}
return 0;
}
ERROR:
ERROR:MDT - Section .bss contents (0x1ee8-0x427) does not completely fit into
memory dlmb_cntlr (0x0-0x1fff)
ERROR:MDT -
Elf file just.elf had errors. To build a correct elf file, use Linker script
generator to assist in generating the right linker script and use the same
for building the elf file.

你现在的程序是放在lmb里面的，所以不能completely fit into
memory dlmb_cntlr。建议在generate linkscript里面把程序的存储位置放到ＤＤＲ里面去。
另外浮点运算对硬件来说很麻烦，建议你在ＭＢ的选项中使用ＦＰＵ以提高性能

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