在 ISE 10.1用生成乘法器ＩＰ核的问题

前辈们好，

我写了一个简单的Ｖｅｒｉｌｏｇ程序，里面用到ＩＰ核乘法器，在Ｍｏｄｅｌｓｉｍ中进行仿真时，出现了下面的问题，我实在不知道是什么原因，只好向各位请教了。我的ＩＳＥ是１０．１版本的，Ｍｏｄｅｌｓｉｍ是６．３ｃ的。

# ** Note: (vsim-3812) Design is being optimized...
# ** Error: mult.v(85): Module 'CMPY_V2_1' is not defined.
# ** Error: ct.v(87): Module 'VCC' is not defined.
# ** Error: ct.v(90): Module 'GND' is not defined.
# ** Error: ct.v(94): Module 'INV' is not defined.
# ** Error: ct.v(100): Module 'LUT1' is not defined.
# ** Error: ct.v(106): Module 'LUT1' is not defined.
# ** Error: ct.v(112): Module 'LUT1' is not defined.
# ** Error: ct.v(118): Module 'LUT1' is not defined.
# ** Error: ct.v(124): Module 'LUT1' is not defined.
# ** Error: ct.v(130): Module 'LUT1' is not defined.
# ** Error: ct.v(136): Module 'LUT1' is not defined.
# ** Error: ct.v(142): Module 'LUT1' is not defined.
# ** Error: ct.v(148): Module 'LUT1' is not defined.
# ** Error: ct.v(154): Module 'LUT1' is not defined.
# ** Error: ct.v(160): Module 'LUT1' is not defined.
# ** Error: ct.v(166): Module 'LUT1' is not defined.
# ** Error: ct.v(172): Module 'LUT1' is not defined.
# ** Error: ct.v(178): Module 'LUT1' is not defined.
# ** Error: ct.v(184): Module 'LUT1' is not defined.
# ** Error: ct.v(190): Module 'MUXCY' is not defined.
# ** Error: ct.v(195): Module 'XORCY' is not defined.
# ** Error: ct.v(200): Module 'XORCY' is not defined.
# ** Error: ct.v(206): Module 'MUXCY' is not defined.
# ** Error: ct.v(211): Module 'XORCY' is not defined.
# ** Error: ct.v(217): Module 'MUXCY' is not defined.
# ** Error: ct.v(222): Module 'XORCY' is not defined.
# ** Error: ct.v(228): Module 'MUXCY' is not defined.
# ** Error: ct.v(233): Module 'XORCY' is not defined.
# ** Error: ct.v(239): Module 'MUXCY' is not defined.
# ** Error: ct.v(244): Module 'XORCY' is not defined.
# ** Error: ct.v(250): Module 'MUXCY' is not defined.
# ** Error: ct.v(255): Module 'XORCY' is not defined.
# ** Error: ct.v(261): Module 'MUXCY' is not defined.
# ** Error: ct.v(266): Module 'XORCY' is not defined.
# ** Error: ct.v(272): Module 'MUXCY' is not defined.
# ** Error: ct.v(277): Module 'XORCY' is not defined.
# ** Error: ct.v(283): Module 'MUXCY' is not defined.
# ** Error: ct.v(288): Module 'XORCY' is not defined.
# ** Error: ct.v(294): Module 'MUXCY' is not defined.
# ** Error: ct.v(299): Module 'XORCY' is not defined.
# ** Error: ct.v(305): Module 'MUXCY' is not defined.
# ** Error: ct.v(310): Module 'XORCY' is not defined.
# ** Error: ct.v(316): Module 'MUXCY' is not defined.
# ** Error: ct.v(321): Module 'XORCY' is not defined.
# ** Error: ct.v(327): Module 'MUXCY' is not defined.
# ** Error: ct.v(332): Module 'XORCY' is not defined.
# ** Error: ct.v(338): Module 'MUXCY' is not defined.
# ** Error: ct.v(343): Module 'XORCY' is not defined.
# ** Error: ct.v(349): Module 'MUXCY' is not defined.
# ** Error: ct.v(354): Module 'XORCY' is not defined.
# ** Error: ct.v(362): Module 'FDE' is not defined.
# ** Error: ct.v(370): Module 'FDE' is not defined.
# ** Error: ct.v(378): Module 'FDE' is not defined.
# ** Error: ct.v(386): Module 'FDE' is not defined.
# ** Error: ct.v(394): Module 'FDE' is not defined.
# ** Error: ct.v(402): Module 'FDE' is not defined.
# ** Error: ct.v(410): Module 'FDE' is not defined.
# ** Error: ct.v(418): Module 'FDE' is not defined.
# ** Error: ct.v(426): Module 'FDE' is not defined.
# ** Error: ct.v(434): Module 'FDE' is not defined.
# ** Error: ct.v(442): Module 'FDE' is not defined.
# ** Error: ct.v(450): Module 'FDE' is not defined.
# ** Error: ct.v(458): Module 'FDE' is not defined.
# ** Error: ct.v(466): Module 'FDE' is not defined.
# ** Error: ct.v(474): Module 'FDE' is not defined.
# ** Error: ct.v(482): Module 'FDE' is not defined.
# ** Error: ct.v(485): Module 'VCC' is not defined.
# ** Error: ct.v(488): Module 'GND' is not defined.
# Optimization failed
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./test_one2two.fdo PAUSED at line 10

我不是非常清楚,不过貌似你的modelsim里没有Xilinx的库, 比如LUT1这个元件应该是FPGA里的, 你可能需要在modelsim重新编译Xilinx的库,或者我记得有ModelSim是Xilinx订制过的, 你可以到Xilinx网站上找一下他订制过的那个ModelSim.

你好，谢谢你的回复，我看了一下，我的Ｍｉｄｅｌｓｉｍ中的Ｘｉｌｉｎｘ库已经译过了，而且还加载到了Ｍｏｄｅｌｓｉｍ中，我在Ｍｏｄｅｌｓｉｍ中进行部分ＩＰ核的仿真是没有问题，但是还有部分的ＩＰ核就出这个问题了，我实在不知怎么办，系统也重新装过了，ＩＳＥ软件安装时全部都装了，但是就是出这个问题，。。。。

这个问题已经解决，谢谢大家的指导了，现拿出来大家共享吧：
解决方法：Modelsim中对Verlog的库是自动加载的，但是对VHdl的库是不能自动加载的，我知道为什么这样，但是，如果在ISE中设置了第三方的仿真工具不Modelsim而从ISE中直接启动Modelsim的话，其中的Vhdl编译库要重新加载一下，因为在WordSpace中对*.V的文件进行仿真时，你看一下他的仿真库就知道了，里面只有几个Verilog的库，而没有Vhdl的库，所以重新加载一下问题就解决了。

需要重新加载？貌似我没有碰到这个问题哦，都是直接仿真就OK，我用的是modelsim6.5