利用MPMC核设计DDR2内存控制器

利用MPMC核自己设计了一个DDR2内存控制器，并采用NPI接口向DDR2内读写数据；

在验证NPI接口能否正确读入数据时，设计了一个FIFO（32位输入，64位输出）以向NPI接口送数据（数据为连续递增的），然而DOWNLOAD后，却发现DDR2内存地址里面的数据并不是想要的数据，而且数据没有变化；

我用的ML507的开发板，FPGA是V5的

请教高手几个问题：

1. 关于MPMC内核的问题：内核的工作时钟是100M么？他产生的125M（分别有0和90度相移）和200M时钟是有什么用途？

2. FIFO的时钟应该怎么样设计，我选用了125M的时钟，而且我的NPI控制模块（控制NPI读写）的时钟也是125M的，不知道问题是不是出在此？

望高手给小弟指导指导

这是MHS文件：
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
# Tue Aug 18 11:03:10 2009
# Target Board: Custom
# Family: virtex5
# Device: xc5vfx70t
# Package: ff1136
# Speed Grade: -1
# Processor: microblaze_0
# System clock frequency: 125.00 MHz
# On Chip Memory : 16 KB
# ##############################################################################
PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_ODT, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Addr, DIR = O, VEC = [12:0]
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_BankAddr_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_BankAddr, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CAS_n, DIR = O
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE, DIR = O, VEC = [0:0]
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n, DIR = O, VEC = [0:0]
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_RAS_n, DIR = O
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_WE_n, DIR = O
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DM_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DM, DIR = O, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS, DIR = IO, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_n, DIR = IO, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQ = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQ, DIR = IO, VEC = [63:0]
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_n, DIR = O, VEC = [1:0]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
PORT NPI_Addr = PIM1_Addr, DIR = I, VEC = [31:0]
PORT NPI_AddrReq = PIM1_AddrReq, DIR = I
PORT NPI_RNW = PIM1_RNW, DIR = I
PORT NPI_Size = PIM1_Size, DIR = I, VEC = [3:0]
PORT NPI_RdModWr = PIM1_RdModWr, DIR = I
PORT NPI_InitDone = PIM1_InitDone, DIR = O
PORT NPI_AddrAck = PIM1_AddrAck, DIR = O
PORT NPI_WrFIFO_Data = PIM1_WrFIFO_Data, DIR = I, VEC = [63:0]
PORT NPI_WrFIFO_BE = PIM1_WrFIFO_BE, DIR = I, VEC = [7:0]
PORT NPI_WrFIFO_Push = PIM1_WrFIFO_Push, DIR = I
PORT NPI_WrFIFO_Flush = PIM1_WrFIFO_Flush, DIR = I
PORT NPI_WrFIFO_Empty = PIM1_WrFIFO_Empty, DIR = O
PORT NPI_WrFIFO_AlmostFull = PIM1_WrFIFO_AlmostFull, DIR = O
PORT NPI_RdFIFO_Pop = PIM1_RdFIFO_Pop, DIR = I
PORT NPI_RdFIFO_Flush = PIM1_RdFIFO_Flush, DIR = I
PORT NPI_RdFIFO_Data = PIM1_RdFIFO_Data, DIR = O, VEC = [63:0]
PORT NPI_RdFIFO_RdWdAddr = PIM1_RdFIFO_RdWdAddr, DIR = O, VEC = [3:0]
PORT NPI_RdFIFO_Empty = PIM1_RdFIFO_Empty, DIR = O
PORT NPI_RdFIFO_Latency = PIM1_RdFIFO_Latency, DIR = O, VEC = [1:0]
PORT Clk125M = DDR2_SDRAM_W1D32M72R8A_5A_mpmc_clk_90_s, DIR = O, SIGIS = CLK, CLK_FREQ = 125000000

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_INTERCONNECT = 1
PARAMETER HW_VER = 7.10.d
PARAMETER C_DEBUG_ENABLED = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_dbg
PORT MB_RESET = mb_reset
END
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.03.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00003fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN xps_uartlite
PARAMETER INSTANCE = RS232
PARAMETER HW_VER = 1.00.a
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_SPLB_CLK_FREQ_HZ = 125000000
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_RX
PORT TX = fpga_0_RS232_TX
END
BEGIN util_bus_split
PARAMETER INSTANCE = DDR2_SDRAM_W1D32M72R8A_5A_util_bus_split_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 2
PARAMETER C_LEFT_POS = 0
PARAMETER C_SPLIT = 1
PORT Sig = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE_split
PORT Out2 = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE
END
BEGIN util_bus_split
PARAMETER INSTANCE = DDR2_SDRAM_W1D32M72R8A_5A_util_bus_split_1
PARAMETER HW_VER = 1.00.a
PARAMETER C_SIZE_IN = 2
PARAMETER C_LEFT_POS = 0
PARAMETER C_SPLIT = 1
PORT Sig = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n_split
PORT Out2 = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 125000000
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT1_FREQ = 125000000
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT1_PHASE = 90
PARAMETER C_CLKOUT1_GROUP = PLL0
PARAMETER C_CLKOUT2_FREQ = 200000000
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = NONE
PARAMETER C_CLKOUT3_FREQ = 62500000
PARAMETER C_CLKOUT3_BUF = TRUE
PARAMETER C_CLKOUT3_PHASE = 0
PARAMETER C_CLKOUT3_GROUP = NONE
PORT CLKOUT0 = sys_clk_s
PORT CLKOUT1 = DDR2_SDRAM_W1D32M72R8A_5A_mpmc_clk_90_s
PORT CLKOUT2 = clk_200mhz_s
PORT CLKOUT3 = DDR2_SDRAM_W1D32M72R8A_5A_MPMC_Clk_Div2
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
END
BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 1.00.d
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Peripheral_Reset = sys_periph_reset
END
BEGIN mpmc
PARAMETER INSTANCE = DDR2_SDRAM_W1D32M72R8A_5A
PARAMETER HW_VER = 4.03.a
PARAMETER C_NUM_PORTS = 2
PARAMETER C_MEM_PARTNO = MT4HTF3264H-53E
PARAMETER C_MPMC_CLK0_PERIOD_PS = 8000
PARAMETER C_MEM_DQS_IO_COL = 0x000000000000000000
PARAMETER C_MEM_DQ_IO_MS = 0b00000000_01110101_00111101_00001111_00011110_00101110_11000011_11000001_10111100
PARAMETER C_MEM_ODT_TYPE = 1
PARAMETER C_MEM_CE_WIDTH = 2
PARAMETER C_MEM_ODT_WIDTH = 2
PARAMETER C_MEM_CLK_WIDTH = 2
PARAMETER C_MEM_CS_N_WIDTH = 2
PARAMETER C_NUM_IDELAYCTRL = 3
PARAMETER C_MEM_REG_DIMM = 0
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
PARAMETER C_MPMC_BASEADDR = 0x90000000
PARAMETER C_MPMC_HIGHADDR = 0x9FFFFFFF
PARAMETER C_PIM1_BASETYPE = 4
BUS_INTERFACE SPLB0 = mb_plb
PORT DDR2_ODT = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_ODT
PORT DDR2_Addr = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Addr
PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_BankAddr
PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CAS_n
PORT DDR2_CE = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CE_split
PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_CS_n_split
PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_RAS_n
PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_WE_n
PORT DDR2_DM = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DM
PORT DDR2_DQS = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS
PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQS_n
PORT DDR2_DQ = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_DQ
PORT DDR2_Clk = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk
PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_W1D32M72R8A_5A_DDR2_Clk_n
PORT MPMC_Clk0 = sys_clk_s
PORT MPMC_Clk90 = DDR2_SDRAM_W1D32M72R8A_5A_mpmc_clk_90_s
PORT MPMC_Clk_200MHz = clk_200mhz_s
PORT MPMC_Clk0_DIV2 = DDR2_SDRAM_W1D32M72R8A_5A_MPMC_Clk_Div2
PORT MPMC_Rst = sys_periph_reset
PORT PIM1_Addr = PIM1_Addr
PORT PIM1_AddrReq = PIM1_AddrReq
PORT PIM1_RNW = PIM1_RNW
PORT PIM1_Size = PIM1_Size
PORT PIM1_RdModWr = PIM1_RdModWr
PORT PIM1_InitDone = PIM1_InitDone
PORT PIM1_AddrAck = PIM1_AddrAck
PORT PIM1_WrFIFO_Data = PIM1_WrFIFO_Data
PORT PIM1_WrFIFO_BE = PIM1_WrFIFO_BE
PORT PIM1_WrFIFO_Push = PIM1_WrFIFO_Push
PORT PIM1_WrFIFO_Flush = PIM1_WrFIFO_Flush
PORT PIM1_WrFIFO_Empty = PIM1_WrFIFO_Empty
PORT PIM1_WrFIFO_AlmostFull = PIM1_WrFIFO_AlmostFull
PORT PIM1_RdFIFO_Pop = PIM1_RdFIFO_Pop
PORT PIM1_RdFIFO_Flush = PIM1_RdFIFO_Flush
PORT PIM1_RdFIFO_Data = PIM1_RdFIFO_Data
PORT PIM1_RdFIFO_RdWdAddr = PIM1_RdFIFO_RdWdAddr
PORT PIM1_RdFIFO_Empty = PIM1_RdFIFO_Empty
PORT PIM1_RdFIFO_Latency = PIM1_RdFIFO_Latency
END
 

打红色的这几个信号有什么用途？

你的ddr2的电路是否正常？