edk中添加ip核出现错误

Parsing PAO project file successfully ...
Analyzing HDL source files ...
Analyzing HDL source files successfully ...
HDL language for the peripheral (top level) design unit opb_ac97 is vhdl ...
INFO:MDT - Create temparary xst project file:
   I:\edklabs\lab1\pcores/opb_ac97_v1_00_a.prj
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_timing.vhd
" in Library opb_ac97_v2_00_a.
Entity <ac97_timing> compiled.
Entity <ac97_timing> (Architecture <IMP>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/srl_fifo.vhd"
in Library opb_ac97_v2_00_a.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/bram_fifo.vhd"
in Library opb_ac97_v2_00_a.
Entity <BRAM_FIFO> compiled.
Entity <BRAM_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_core.vhd"
in Library opb_ac97_v2_00_a.
Entity <ac97_core> compiled.
Entity <ac97_core> (Architecture <IMP>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_fifo.vhd"
in Library opb_ac97_v2_00_a.
Entity <ac97_fifo> compiled.
Entity <ac97_fifo> (Architecture <IMP>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd" in
Library common_v1_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/opb_ac97.vhd"
in Library opb_ac97_v2_00_a.
Entity <opb_ac97> compiled.
Entity <opb_ac97> (Architecture <IMP>) compiled.

Analyzing HDL attributes ...
ERROR:MDT - Could not find top level entity opb_ac97_v1_00_a
WARNING:MDT - Unable to delete temparary project file
   I:\edklabs\lab1\pcores\opb_ac97_v1_00_a.prj : 13
HDL language for the peripheral (top level) design unit opb_ac97 is vhdl ...
WARNING:MDT - Project file I:\edklabs\lab1\pcores/opb_ac97_v1_00_a.prj already
   exists, will be overwrite and removed afterward ...
INFO:MDT - Create temparary xst project file:
   I:\edklabs\lab1\pcores/opb_ac97_v1_00_a.prj
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_timing.vhd
" in Library opb_ac97_v2_00_a.
Entity <ac97_timing> compiled.
Entity <ac97_timing> (Architecture <IMP>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/srl_fifo.vhd"
in Library opb_ac97_v2_00_a.
Entity <SRL_FIFO> compiled.
Entity <SRL_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/bram_fifo.vhd"
in Library opb_ac97_v2_00_a.
Entity <BRAM_FIFO> compiled.
Entity <BRAM_FIFO> (Architecture <IMP>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_core.vhd"
in Library opb_ac97_v2_00_a.
Entity <ac97_core> compiled.
Entity <ac97_core> (Architecture <IMP>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/ac97_fifo.vhd"
in Library opb_ac97_v2_00_a.
Entity <ac97_fifo> compiled.
Entity <ac97_fifo> (Architecture <IMP>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/common_v1_00_a/hdl/vhdl/pselect.vhd" in
Library common_v1_00_a.
Entity <pselect> compiled.
Entity <pselect> (Architecture <imp>) compiled.
Compiling vhdl file
"I:/edk/hw/XilinxProcessorIPLib/pcores/opb_ac97_v2_00_a/hdl/vhdl/opb_ac97.vhd"
in Library opb_ac97_v2_00_a.
Entity <opb_ac97> compiled.
Entity <opb_ac97> (Architecture <IMP>) compiled.

Analyzing HDL attributes ...
ERROR:MDT - Could not find top level entity opb_ac97_v1_00_a
WARNING:MDT - Unable to delete temparary project file
   I:\edklabs\lab1\pcores\opb_ac97_v1_00_a.prj : 13

请问这是什么原因呢？该怎么解决

ok
你是不是在重新导入这个IP核呢？
问题是：
ERROR:MDT - Could not find top level entity opb_ac97_v1_00_a

当然情况不是因为你的所有文件中没有top文件，而是：
你的top module的名字，和top module所在文件的名字，你IP去掉版本号之后的名字不一致。机器很笨的。你需要很好的比配这些名字。比如你这里的名字应该是opb_ac97。所以你可以采用以下两种方式：
1）把我刚刚说到的三个东西的名字都修改成一样的。
2)把你的top module所在的文件，放到你源文件列表的最下方。（在导入IP的时候，有一个界面是你这个IP所有的源文件，VHDL也好，Verilog也好）将那个含有top module的放到这些文件列表的最下方。

受教了。

谢谢 我试试

我刚刚试了但还是出现一样的错误，这到底是什么原因呢？下载的ip核是不是还要经过什么处理呢？我下载的ml403的

那么说一下你的目的吧。
我可以想到两种情况
1）你要用这个IP？直接放到pcores下，重新打开edk就可以使用了。
2）你要重新导入这个ip，比如你觉得他版本号不好，需要换一个。等等。
一般，你要是只是用的话，不需要重新导入的。只需要在你edk工程的目录下pcores下放你的这个ac97的ip就好了。

我现在用的是Virtex II pro这个开发板，我建工程的时候在向导和ip catalog中也没有找到ps2 和ac97以及tft 控制器，所以想添加进去，但是现在总是用不了，我用了你说的方法试了但还是不行，我放在了我的工程下面的pcores下面 但是从新打开工程后也没有看见那个核！

我又重新试了一下，终于可以了用了
我还有个我能提想问一下就是当我要添加其他的ip核的时候比如说ps2 port和tft controller的时候是不是要找和我的板搭配的核，还是说我用ml403的也可以呢？因为我找不到xilinx Virtex II pro的相关ip核
谢谢！

怎么好的呢？

 

 

IP跟板子没有太大关系

估计是工程问题，我重新建立一个工程然后在按照你说的添加进到我的pcores里面，现在就可以见到我要的ip核了！谢谢！

恩，如果要用的话，放到pcores下面就好了。
无需再次重新导入的。

继续做下去发现了下面的错误
ERROR:NgdBuild:604 - logical block
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/WO_ECC.DDR_CTRL_I/WO_ECC_BUS1XDDR.RDDATA_PATH_I/GEN_RD_DATA_BUS1XDDR.FI
FO_GEN[7].V2_ASYNCH_FIFO_I' with type
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' could not
be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' is not
supported in target 'virtex2p'.
ERROR:NgdBuild:604 - logical block
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/WO_ECC.DDR_CTRL_I/WO_ECC_BUS1XDDR.RDDATA_PATH_I/GEN_RD_DATA_BUS1XDDR.FI
FO_GEN[6].V2_ASYNCH_FIFO_I' with type
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' could not
be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' is not
supported in target 'virtex2p'.
ERROR:NgdBuild:604 - logical block
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/WO_ECC.DDR_CTRL_I/WO_ECC_BUS1XDDR.RDDATA_PATH_I/GEN_RD_DATA_BUS1XDDR.FI
FO_GEN[5].V2_ASYNCH_FIFO_I' with type
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' could not
be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' is not
supported in target 'virtex2p'.
ERROR:NgdBuild:604 - logical block
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/WO_ECC.DDR_CTRL_I/WO_ECC_BUS1XDDR.RDDATA_PATH_I/GEN_RD_DATA_BUS1XDDR.FI
FO_GEN[4].V2_ASYNCH_FIFO_I' with type
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' could not
be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' is not
supported in target 'virtex2p'.
ERROR:NgdBuild:604 - logical block
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/WO_ECC.DDR_CTRL_I/WO_ECC_BUS1XDDR.RDDATA_PATH_I/GEN_RD_DATA_BUS1XDDR.FI
FO_GEN[3].V2_ASYNCH_FIFO_I' with type
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' could not
be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' is not
supported in target 'virtex2p'.
ERROR:NgdBuild:604 - logical block
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/WO_ECC.DDR_CTRL_I/WO_ECC_BUS1XDDR.RDDATA_PATH_I/GEN_RD_DATA_BUS1XDDR.FI
FO_GEN[2].V2_ASYNCH_FIFO_I' with type
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' could not
be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' is not
supported in target 'virtex2p'.
ERROR:NgdBuild:604 - logical block
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/WO_ECC.DDR_CTRL_I/WO_ECC_BUS1XDDR.RDDATA_PATH_I/GEN_RD_DATA_BUS1XDDR.FI
FO_GEN[1].V2_ASYNCH_FIFO_I' with type
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' could not
be resolved. A pin name misspelling can cause this, a missing edif or ngc
file, or the misspelling of a type name. Symbol
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' is not
supported in target 'virtex2p'.
ERROR:NgdBuild:604 - logical block
'ddr_256mb_32mx64_rank1_row13_col10_cl2_5/ddr_256mb_32mx64_rank1_row13_col10_
cl2_5/WO_ECC.DDR_CTRL_I/WO_ECC_BUS1XDDR.RDDATA_PATH_I/GEN_RD_DATA_BUS1X
WARNING:NgdBuild:443 - SFF primitive
'opb_intc_0/opb_intc_0/OPB_INTFC_I/OPB_ABUS_REG_GEN[4].OPB_ABUS_REG_BIT_I'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'opb_intc_0/opb_intc_0/OPB_INTFC_I/OPB_ABUS_REG_GEN[3].OPB_ABUS_REG_BIT_I'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'opb_intc_0/opb_intc_0/OPB_INTFC_I/OPB_ABUS_REG_GEN[2].OPB_ABUS_REG_BIT_I'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'opb_intc_0/opb_intc_0/OPB_INTFC_I/OPB_ABUS_REG_GEN[1].OPB_ABUS_REG_BIT_I'
has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
'opb_intc_0/opb_intc_0/OPB_INTFC_I/OPB_ABUS_REG_GEN[0].OPB_ABUS_REG_BIT_I'
has unconnected output pin
WARNING:NgdBuild:486 - Attribute "INIT" is not allowed on symbol
"plb_tft_cntlr_ref_0/TFT_IF_U5/TFT_CLK_ODDR" of type "ODDR". This attribute
will be ignored.
ERROR:NgdBuild:604 - logical block
'plb_tft_cntlr_ref_0/plb_tft_cntlr_ref_0/TFT_IF_U5/TFT_CLK_ODDR' with type
'ODDR' could not be resolved. A pin name misspelling can cause this, a
missing edif or ngc file, or the misspelling of a type name. Symbol 'ODDR' is
not supported in target 'virtex2p'.
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 9
Number of warnings: 181

One or more errors were found during NGDBUILD. No NGD file will be written.
Writing NGDBUILD log file "system.bld"...
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...

里面好像有说到我的ip核不支持xup2p板 是不是这个原因，还有就是有很多的warning 都是说什么没有连接output pin的 为什么是这样的

'ddr_256mb_32mx64_rank1_row13_col10_cl2_5_wrapper_async_fifo_v4_0' is not
supported in target 'virtex2p'
好像不支持

你的问题解决了吗！！ 我在做这方面的工作！可以探讨一下！我这DDR256可以使用！

问一下！你的ac97的IP核添加成功了吗！我的也添加出现了错误！谢谢！！！

看看

最后如何？啊啊啊啊啊啊啊啊啊啊啊啊啊