关于使用MPMC的问题

各位大侠，小弟目前在做一个这样子的实验，所用实验板采用Spartan3adsp3400A的FPGA芯片，LPDDR的内存，和两片SST的39VF3201的NOR flash。我想在FPGA上运行MICROBLAZE，以LPDDR内存，可是建立完BSB后，运行外设测试的程序，程序检测外设失败。我对MPMC的参数设置都是根据LPDDR内存芯片提供的DATASHEET设置。

各位大侠，小弟是否还有哪个地方没有设置好？或Spartan3A dsp不支持LPDDR呢？

关于DDR部分的MHS如下：

BEGIN mpmc
 PARAMETER INSTANCE = DDR_SDRAM
 PARAMETER C_NUM_PORTS = 2
 PARAMETER C_USE_MIG_S3_PHY = 1
 PARAMETER C_SPECIAL_BOARD = S3E_1600E
 PARAMETER C_MEM_TYPE = DDR
 PARAMETER C_MEM_PARTNO = CUSTOM
 PARAMETER C_MEM_DATA_WIDTH = 32
 PARAMETER C_PIM0_BASETYPE = 1
 PARAMETER C_XCL0_B_IN_USE = 1
 PARAMETER HW_VER = 6.00.a
 PARAMETER C_USE_MIG_FLOW = 1
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 12000
 PARAMETER C_PIM1_BASETYPE = 2
 PARAMETER C_MEM_REDUCED_DRV = 0
 PARAMETER C_MEM_PART_DATA_DEPTH = 32
 PARAMETER C_MEM_PART_DATA_WIDTH = 32
 PARAMETER C_MEM_PART_NUM_BANK_BITS = 2
 PARAMETER C_MEM_PART_NUM_ROW_BITS = 13
 PARAMETER C_MEM_PART_NUM_COL_BITS = 9
 PARAMETER C_MEM_PART_CAS_A_FMAX = 83
 PARAMETER C_MEM_PART_CAS_B_FMAX = 83
 PARAMETER C_MEM_PART_CAS_A = 2
 PARAMETER C_MEM_PART_CAS_B = 3
 PARAMETER C_MEM_PART_TRRD = 12000
 PARAMETER C_MEM_PART_TRCD = 18000
 PARAMETER C_MEM_PART_TWR = 12000
 PARAMETER C_MEM_PART_TREFI = 7800000
 PARAMETER C_MEM_PART_TRFC = 70000
 PARAMETER C_MEM_PART_TRP = 18000
 PARAMETER C_MEM_PART_TRC = 60000
 PARAMETER C_MEM_PART_TRASMAX = 70000000
 PARAMETER C_MEM_PART_TRAS = 42000
 PARAMETER C_SPLB1_NATIVE_DWIDTH = 32
 PARAMETER C_MPMC_BASEADDR = 0x8C000000
 PARAMETER C_MPMC_HIGHADDR = 0x8FFFFFFF
 BUS_INTERFACE SPLB1 = mb_plb
 BUS_INTERFACE XCL0 = microblaze_0_DXCL
 BUS_INTERFACE XCL0_B = microblaze_0_IXCL
 PORT MPMC_Clk0 = clk_50_0000MHz
 PORT MPMC_Clk90 = clk_50_0000MHz_90
 PORT MPMC_Rst = sys_periph_reset
 PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pin
 PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pin
 PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pin
 PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pin
 PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pin
 PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pin
 PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pin
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pin
 PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pin
 PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pin
 PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pin
 PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pin
 PORT DDR_DQS_Div_O = DDR_SDRAM_DDR_DQS_Div_O_pin
 PORT DDR_DQS_Div_I = DDR_SDRAM_DDR_DQS_Div_I_pin
END
 

PORT MPMC_Clk0 = clk_50_0000MHz
 PORT MPMC_Clk90 = clk_50_0000MHz_90

这两个信号的相位差 很重要

你改为 120 180 等

再试试