When I am using Export to program an FPGA I receive the error
"startup clock for this file is CCLK instead of JTAG-CLK, problems
will likely occur." What do I do?
The configuration state machine inside the FPGA needs a "startup
clock" to clock the final startup sequence after configuration.
This clock source is controlled by a bit in the binary
configuration file (.bit file). The startup clock source is
controlled by an option setting in the "Generate Program File"
process in the Xilinx ISE Foundation or Xilinx ISE WebPACK Project
Navigator tool. The clock source should be set to JTAG to create a
.bit file to be used for configuring the FPGA using a JTAG
interface. The clock source should be set to CCLK for .bit files
that are intended to be programmed into a Platform Flash ROM.
When building the project make sure that the startup clock is set
appropriately. You can do this in Project Navigator by right
clicking on the "Generate Program File" process. Select Properties
and then click Startup Options. Set the startup clock to JTAG or
CCLK as appropriate.
The Xilinx iMPACT tool is capable of automatically setting the
statup clock bit to JTAG if necessary during the programming
process. Export, the Digilent Adept Suite programming tool, isn't
capable of changing the clock source "on the fly" and the
programming file must be built with the correct setting.
当前离线
