Addressable Shift Register

The Xilinx Addressable Shift Register block is a variable-length shift
register in which any register in the delay chain can be addressed and
driven onto the output data port.
变长移位寄存器链，链中每个寄存器的值可以被地址索引读取
The block operation is most easily thought of as a chain of registers,
where each register output drives an input to a multiplexer, as shown
below. The multiplexer select line is driven by the address port (addr). The output data
port is shown below as q.
移位寄存器链中的输出驱动与复用器，复用器用地址addr寻址输出

post starter! please give a example for this module