求助：edk bootloader问题

在用edk 生成booltloader时出现如下问题，始终没弄明白问题在什么地方，请路过的高手指点指点，谢谢！
TAG chain configuration
--------------------------------------------------
Device ID Code IR Length Part Name
1 21c3a093 6 XC3S1600E
2 f5046093 8 XCF04S
3 f5046093 8 XCF04S
4 06e5e093 8 XC2C64A_VQ44_1532
Error Executing xmd Script : d:/setup/EDK92i/data/xmd/flashwriter.tcl
Error :: ERROR: Could Not Detect MDM Peripheral on Hardware. Check:
1. If FPGA is Configured Correctly
2. MDM Core is Instantiated in the Design

Done!

你的工程里没有MDM？

 有，我看过了，下面是MHS


PARAMETER VERSION = 2.1.0

 PORT fpga_0_RS232_DTE_RX_pin = fpga_0_RS232_DTE_RX, DIR = I
 PORT fpga_0_RS232_DTE_TX_pin = fpga_0_RS232_DTE_TX, DIR = O
 PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN, DIR = O
 PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN, DIR = O, VEC = [0:0]
 PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN, DIR = O
 PORT fpga_0_FLASH_emc_ben_gnd_pin = net_gnd, DIR = O
 PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A, DIR = O, VEC = [8:31]
 PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ, DIR = IO, VEC = [0:7]
 PORT fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O, DIR = IO
 PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [15:0]
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_INTERCONNECT = 1
 PARAMETER HW_VER = 7.00.b
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_AREA_OPTIMIZED = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_dbg
 PORT MB_RESET = mb_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.00.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_DTE
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_DTE_RX
 PORT TX = fpga_0_RS232_DTE_TX
END

BEGIN xps_mch_emc
 PARAMETER INSTANCE = FLASH
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 8
 PARAMETER C_MEM0_WIDTH = 8
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_SYNCH_MEM_0 = 0
 PARAMETER C_TCEDV_PS_MEM_0 = 110000
 PARAMETER C_TWC_PS_MEM_0 = 110000
 PARAMETER C_TAVDV_PS_MEM_0 = 110000
 PARAMETER C_TWP_PS_MEM_0 = 70000
 PARAMETER C_THZCE_PS_MEM_0 = 35000
 PARAMETER C_TLZWE_PS_MEM_0 = 15000
 PARAMETER C_MEM0_BASEADDR = 0x87000000
 PARAMETER C_MEM0_HIGHADDR = 0x87ffffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Mem_A = fpga_0_FLASH_Mem_A_split
 PORT Mem_DQ = fpga_0_FLASH_Mem_DQ
 PORT Mem_OEN = fpga_0_FLASH_Mem_OEN
 PORT Mem_WEN = fpga_0_FLASH_Mem_WEN
 PORT Mem_CEN = fpga_0_FLASH_Mem_CEN
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR_SDRAM
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_NUM_PORTS = 1
 PARAMETER C_MEM_PARTNO = MT46V32M16-6
 PARAMETER C_SPECIAL_BOARD = S3E_1600E
 PARAMETER C_MEM_DATA_WIDTH = 16
 PARAMETER C_MEM_DQS_WIDTH = 2
 PARAMETER C_MEM_DM_WIDTH = 2
 PARAMETER C_MEM_TYPE = DDR
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
 PARAMETER C_MPMC_BASEADDR = 0x80000000
 PARAMETER C_MPMC_HIGHADDR = 0x83ffffff
 PARAMETER C_SPLB0_NATIVE_DWIDTH = 32
 BUS_INTERFACE SPLB0 = mb_plb
 PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
 PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
 PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
 PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
 PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
 PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
 PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
 PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
 PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
 PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
 PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
 PORT MPMC_Clk0 = DDR_SDRAM_mpmc_clk_s
 PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
 PORT MPMC_Rst = sys_bus_reset
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER C_BASEADDR = 0x85a08000
 PARAMETER C_HIGHADDR = 0x85a09fff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN util_bus_split
 PARAMETER INSTANCE = FLASH_util_bus_split_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 0
 PARAMETER C_SPLIT = 8
 PORT Sig = fpga_0_FLASH_Mem_A_split
 PORT Out2 = fpga_0_FLASH_Mem_A
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 50000000
 PARAMETER C_CLKOUT0_FREQ = 50000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT1_FREQ = 100000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = GROUP0
 PARAMETER C_CLKOUT2_FREQ = 100000000
 PARAMETER C_CLKOUT2_PHASE = 90
 PARAMETER C_CLKOUT2_GROUP = GROUP0
 PORT CLKOUT0 = sys_clk_s
 PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_s
 PORT CLKOUT2 = DDR_SDRAM_mpmc_clk_90_s
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
END

 有，我看过了，下面是MHS


PARAMETER VERSION = 2.1.0

 PORT fpga_0_RS232_DTE_RX_pin = fpga_0_RS232_DTE_RX, DIR = I
 PORT fpga_0_RS232_DTE_TX_pin = fpga_0_RS232_DTE_TX, DIR = O
 PORT fpga_0_FLASH_Mem_OEN_pin = fpga_0_FLASH_Mem_OEN, DIR = O
 PORT fpga_0_FLASH_Mem_CEN_pin = fpga_0_FLASH_Mem_CEN, DIR = O, VEC = [0:0]
 PORT fpga_0_FLASH_Mem_WEN_pin = fpga_0_FLASH_Mem_WEN, DIR = O
 PORT fpga_0_FLASH_emc_ben_gnd_pin = net_gnd, DIR = O
 PORT fpga_0_FLASH_Mem_A_pin = fpga_0_FLASH_Mem_A, DIR = O, VEC = [8:31]
 PORT fpga_0_FLASH_Mem_DQ_pin = fpga_0_FLASH_Mem_DQ, DIR = IO, VEC = [0:7]
 PORT fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O, DIR = IO
 PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr, DIR = O, VEC = [12:0]
 PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n, DIR = O
 PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM, DIR = O, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS, DIR = IO, VEC = [1:0]
 PORT fpga_0_DDR_SDRAM_DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ, DIR = IO, VEC = [15:0]
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST

BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_INTERCONNECT = 1
 PARAMETER HW_VER = 7.00.b
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_AREA_OPTIMIZED = 1
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 BUS_INTERFACE DPLB = mb_plb
 BUS_INTERFACE IPLB = mb_plb
 BUS_INTERFACE DEBUG = microblaze_0_dbg
 PORT MB_RESET = mb_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = mb_plb
 PARAMETER HW_VER = 1.00.a
 PORT PLB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 1.00.a
 PORT LMB_Clk = sys_clk_s
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x00001fff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = RS232_DTE
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BAUDRATE = 9600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_RS232_DTE_RX
 PORT TX = fpga_0_RS232_DTE_TX
END

BEGIN xps_mch_emc
 PARAMETER INSTANCE = FLASH
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MCH_PLB_CLK_PERIOD_PS = 20000
 PARAMETER C_NUM_BANKS_MEM = 1
 PARAMETER C_MAX_MEM_WIDTH = 8
 PARAMETER C_MEM0_WIDTH = 8
 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
 PARAMETER C_SYNCH_MEM_0 = 0
 PARAMETER C_TCEDV_PS_MEM_0 = 110000
 PARAMETER C_TWC_PS_MEM_0 = 110000
 PARAMETER C_TAVDV_PS_MEM_0 = 110000
 PARAMETER C_TWP_PS_MEM_0 = 70000
 PARAMETER C_THZCE_PS_MEM_0 = 35000
 PARAMETER C_TLZWE_PS_MEM_0 = 15000
 PARAMETER C_MEM0_BASEADDR = 0x87000000
 PARAMETER C_MEM0_HIGHADDR = 0x87ffffff
 BUS_INTERFACE SPLB = mb_plb
 PORT Mem_A = fpga_0_FLASH_Mem_A_split
 PORT Mem_DQ = fpga_0_FLASH_Mem_DQ
 PORT Mem_OEN = fpga_0_FLASH_Mem_OEN
 PORT Mem_WEN = fpga_0_FLASH_Mem_WEN
 PORT Mem_CEN = fpga_0_FLASH_Mem_CEN
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR_SDRAM
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_NUM_PORTS = 1
 PARAMETER C_MEM_PARTNO = MT46V32M16-6
 PARAMETER C_SPECIAL_BOARD = S3E_1600E
 PARAMETER C_MEM_DATA_WIDTH = 16
 PARAMETER C_MEM_DQS_WIDTH = 2
 PARAMETER C_MEM_DM_WIDTH = 2
 PARAMETER C_MEM_TYPE = DDR
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER C_MPMC_CLK0_PERIOD_PS = 10000
 PARAMETER C_MPMC_BASEADDR = 0x80000000
 PARAMETER C_MPMC_HIGHADDR = 0x83ffffff
 PARAMETER C_SPLB0_NATIVE_DWIDTH = 32
 BUS_INTERFACE SPLB0 = mb_plb
 PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk
 PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n
 PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr
 PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr
 PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n
 PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE
 PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n
 PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n
 PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n
 PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM
 PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS
 PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ
 PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
 PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_DDR_DQS_Div_I_DDR_SDRAM_DDR_DQS_Div_O
 PORT MPMC_Clk0 = DDR_SDRAM_mpmc_clk_s
 PORT MPMC_Clk90 = DDR_SDRAM_mpmc_clk_90_s
 PORT MPMC_Rst = sys_bus_reset
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER C_BASEADDR = 0x85a08000
 PARAMETER C_HIGHADDR = 0x85a09fff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN bram_block
 PARAMETER INSTANCE = xps_bram_if_cntlr_1_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
END

BEGIN util_bus_split
 PARAMETER INSTANCE = FLASH_util_bus_split_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_SIZE_IN = 32
 PARAMETER C_LEFT_POS = 0
 PARAMETER C_SPLIT = 8
 PORT Sig = fpga_0_FLASH_Mem_A_split
 PORT Out2 = fpga_0_FLASH_Mem_A
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER C_CLKIN_FREQ = 50000000
 PARAMETER C_CLKOUT0_FREQ = 50000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT1_FREQ = 100000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = GROUP0
 PARAMETER C_CLKOUT2_FREQ = 100000000
 PARAMETER C_CLKOUT2_PHASE = 90
 PARAMETER C_CLKOUT2_GROUP = GROUP0
 PORT CLKOUT0 = sys_clk_s
 PORT CLKOUT1 = DDR_SDRAM_mpmc_clk_s
 PORT CLKOUT2 = DDR_SDRAM_mpmc_clk_90_s
 PORT CLKIN = dcm_clk_s
 PORT LOCKED = Dcm_all_locked
 PORT RST = net_gnd
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER C_UART_WIDTH = 8
 PARAMETER C_BASEADDR = 0x84400000
 PARAMETER C_HIGHADDR = 0x8440ffff
 BUS_INTERFACE SPLB = mb_plb
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT Slowest_sync_clk = sys_clk_s
 PORT Dcm_locked = Dcm_all_locked
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
END

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