Features
The PAS5201 is a Gigabit Ethernet Optical Line Terminal (OLT)
system on a chip (SoC) dedicated for use in an Ethernet Passive
Optical Network (IEEE 802.3ah EPON). The PAS5201 chip integrates
Ethernet Media Access Control (MAC) functionality, EPON protocol
management, an advanced classification engine, and an embedded CPU.
An integrated software package provides a complete OLT solution.
PRODUCT BENEFITS
- First-to-market EPON OLT designed for China Telecom specification
- Full IEEE 802.3ah EPON OLT functionality with integrated ARM9 CPU
and comprehensive software package
- Advanced classification engine with support for VLANs, video
services with IP Multicast, IPv4 or IPv6
- Comprehensive OLT software development package with complete set of
device drivers
- FEC coding for improved link budget
| - Integrated encryption enhances security and privacy
- Embedded frame buffers with multiple priority queues and an
optional external packet buffer memory extension
- Run-time programmable dynamic bandwidth allocation (DBA) hardware
engines
- On chip controller performs complete link management and OAM of
EPON link with up to 127 ONUs
|
PRODUCT HIGHLIGHTS
- Gigabit Ethernet PON OLT based on the IEEE 802.3ah standard
- IEEE802.3ah FEC support for improved optical budget and split ratio
- Programmable interface logic for optical transceiver
- Integrated ARM9 CPU subsystem
- Complete integrated hardware and software solution for PON network
control and real-time management
- Complete OLT driver software package development platform.
- Supports automatic operation and OEM extensions
- Support for buffer threshold reporting for compatibility with
dynamic threshold control
- Optional downlink packet buffer extension up to 16 MBytes
- Programmable dynamic bandwidth allocation (DBA) hardware engines
- Algorithms downloadable in runtime
- Multiple algorithms available
| - 8 priority queues with multiprotocol classifier including:
- IEEE802.1q VLAN manipulation and QOS support
- IEEE802.1p priority, IPv6 priority, IPv4 COS
- IGMP
- Full OAM feature set termination according to 802.3ah
- 128 bit AES encryption - downstream and upstream
- IEEE802.1x Authenticator with remote administration
- IEEE802.3x flow control for core network interface
- Dedicated management interface to core network controller
- Configurable traffic rate limiting
|
INTERFACES
- Full duplex transmit and receive EPON port operating at 1.25 Gbps
for connectivity with EPON SERDES devices over TBI
- Flexible optical transceiver control interface for support of
devices from multiple vendors
- Full-duplex Gigabit Ethernet GMII and TBI interface to core network
switch ICs or PHY devices
- Flexible host interface with multiple modes for connectivity to the
core network controller
| - 32-bit CPU memory extension interface for advanced embedded
applications
- Serial EEPROM interface for boot and configuration parameters
- LED indications for the PON, core network and host interfaces
- 4 general-purpose I/O interfaces
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