蓝色忧郁的博客

VHDL 4位MUX的实现,很简单,调试玩玩.

entity mux is
 port(a,b,c,d,sel_0,sel_1:in bit;out_1:out bit);
end mux;

architecture example of mux is
 begin
  process(a,b,c,d,sel_0,sel_1)
   begin
    case bit_vector'(sel_0 & sel_1) is
     when "00" => out_1<=a;
     when "01" => out_1<=b;
     when "10" => out_1<=c;
     when "11" => out_1<=d;
    end case;
  end process;
end example;