collus

在经典的MAC滤波器设计中，系数和数据必须是被存储在一个内存系统中。这里提供了几种存储选项：black RAM、distributed RAM、SRL16E。在实验lab3中选择的是双端口block RAM来存储数据和系数。数据通过周期性数据RAM缓冲器捕获和读出的。所以，该RAM采用混合模式配制。数据是由端口A写入和读出（RAM模式），系数只能从端口B读出（ROM模式）。

该双端口block RAM每个端口的宽度是由输入宽度而定的，并且端口只能是不同如果该宽度是2，4，8，16或者32倍大。数据在进入RAM前和输出RAM后必须调整。

该实验中选择的是block RAM。对于另外两个备选存储器，他们又有什么区别哪？

首先，block RAM和distributed RAM之间的区别：

• 在Xilinx FPGA中，Block RAM是一个专用双端口内存，它含有上千个RAM。FPGA含有多个这样的Blocks；在每一个小的逻辑模块中含有可配置的查找表，它们通常用来做逻辑功能，但是你也可以从新配制成小的RAM，并把小的RAM合并成一个大的RAM，这样组成的RAM称之为distributed RAM。这两种类型的RAM都可以用数据初始化，或者用作ROM。
• BRAM需要时钟信号，DRAM不需要时钟，给定地址就会有数据输出

其次，SRL16E（16-Bit Shift Register Look-Up-Table (LUT) with Clock Enable）。SRL16E是一个移位寄存器查找表。输入端A3、A2、A1和A0选择移位寄存器的输出长度。该移位寄存器长度可能是被确定的，静态长度或者是动态调整的。

The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute. The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaults to a value of four zeros (0000) so that the shift register LUT is cleared during configuration.

The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transition. During subsequent Low-to-High clock transitions data is shifted to the next highest bit position as new data is loaded. The data appears on the Q output when the shift register length determined by the address inputs is reached.

Static Length Mode

To get a fixed length shift register, drive the A3 through A0 inputs with static values. The length of the shift register can vary from 1 bit to 16 bits as determined from the following formula:

Length = (8*A3) +(4*A2) + (2*A1) + A0 +1

If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. If they are all ones (1111), it is 16 bits long.

Dynamic Length Mode

The length of the shift register can be changed dynamically by changing the values driving the A3 through A0 inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), the length of the shift register changes from 16 bits to 8 bits.

Internally, the length of the shift register is always 16 bits and the input lines A3 through A0 select which of the 16 bits reach the output.

Usage

Below are example templates for instantiating this component into a design. These templates can be cut and pasteddirectly into the user’s source code.

VHDL Instantiation Templates

-- SRL16: 16-bit shift register LUT operating on posedge of clock
--        All FPGAs
-- Xilinx  HDL Libraries Guide version 7.1i

   SRL16_inst : SRL16
-- The following generic declaration is only necessary if you wish
to
-- change the initial contents of the SRL to anything other than
all
-- zero's.
   generic map (
      INIT => X"0000")
   port map (
      Q => Q,       -- SRL data output
      A0 => A0,     -- Select[0] input
      A1 => A1,     -- Select[1] input
      A2 => A2,     -- Select[2] input
      A3 => A3,     -- Select[3] input
      CLK => CLK,   -- Clock input
      D => D        -- SRL data input
   );


-- End of SRL16_inst instantiation

Verilog Instantiation Template

-- SRL16: 16-bit shift register LUT operating on posedge of clock
--        All FPGAs
-- Xilinx  HDL Libraries Guide version 7.1i

   SSRL16 SRL16_inst (
      .Q(Q),       // SRL data output
      .A0(A0),     // Select[0] input
      .A1(A1),     // Select[1] input
      .A2(A2),     // Select[2] input
      .A3(A3),     // Select[3] input
      .CLK(CLK),   // Clock input
      .D(D)        // SRL data input
   );

// The following defparam declaration is only necessary if you wish
to
// change the initial contents of the SRL to anything other than
all
// zero's.  If the instance name to the SRL is changed, that change
// needs to be reflected in the defparam statements.

   defparam SRL16_inst.INIT = 16'h0000;


// End of SRL16_inst instantiation

Commonly Used Constraints

BEL, U_SET, INIT