What is Verilog?
IEEE industry standard Hardware Description Language(HDL) - used to
describe a digital system; For both Simulation & Synthesis.
Verilog History
Introduced in 1984 by Gateway Design Auatomation; 1989 Cadence purchased Gaateway (Verilog-XL similator); 1990 Cadence released Verilog to the public; Open Verilog International(OVI) was formed to control the language specifications; 1993 OVI released version 2.0; 1993 IEEE accepdt OVI Verilog as a standard,Verilog 1364
Verilog Structure
Verilog HDL: Consists of Keywords,syntax and semantics used to describe hardware functionality and timing; PLI: Programming Language Interface provides C language routines used to interact between Verilog and EDA tools.(Simulators,Waveform displays);SDF: Standard Delay Format - a file used to backannotate timing information to simulators and other tools.
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