MF RC500-高集成ISO14443A 读卡器设计（第四部分：天线与软件）dongxl 原创
一 MF RC500 匹配电路和天线的设计
1.1 基本设计规则
MF RC500 是一个单独的读卡器集成电路它要求在没有外部放大器的情况下工作距离达到100mm。
剩下的无源RF 部分的设计很简单明了首先要确定哪个可行的基本概念最能符合应用的要求。
设计帮助会对这个决定作出支持两个不同的概念可以设计一个天线和一个匹配电路。
• 直接匹配的天线用读卡器和天线的最小距离可以建立一个小型的完整终端可行的应用是一个小型建筑物的访问控制读卡器或者是手持的读卡器。
• 500
匹配的天线可以作为读卡器和天线之间用长距离同轴电缆连接的应用的一个简单的解决方案连接读卡器匹配电路和天线的同轴电缆最长距离可达10m。
图1：天线设计与环境影响
1.2 估算最合适的天线大小
MIFARE®系统的工作距离由下面几个因素决定
• 读卡器的天线大小
• 给定天线的匹配电路品质
• 环境的影响
下一个设计步骤是由天线的大小估计工作距离完整的计算可以在附录A 中找到
MIFARE®卡由读卡器产生的磁通供电卡集成电路可以获得的能量随读卡器天线和卡之间的距离不同。
而变化在2.3
节已经提到MIFARE®系统使用变压器原理描述变压器的一个重要的参数是耦合系数k。它可被定义为与读卡器线圈和卡线圈之间的距离以及与读卡器天线和卡线圈的大小有关的一个几何参数，假设标准应用中MIFARE®卡有卡芯片的尺寸卡的线圈的尺寸是固定的。
计算使用的是环形的天线如果实际使用的是矩形或方形的天线可以用有相等面积的环形天线来估算。
图2：天线的匹配设置
2.1 确定天线的等效电路
读卡器的天线线圈可以用图3.4
左边的等效电路表示建议设计的直接匹配天线的天线线圈，应当有一个接地的中心抽头这个中心抽头是用于改善天线线圈的EMC
性能线圈本身可以用电感La 和Lb 表示。
电阻Ra 和Rb 表示电阻损耗并联的Ca 和Cb 表示电容损耗由于La 和Lb 之间有耦合作用。
图3：滤波与谐振电路的元件值
2.2 品质因子Q
根据天线的几何形状Q 的值通常在50 100 之间要进行正确的数据传输这个值还要减少。MIFARE®的波特率是105.9kHz/sec
数据从RWD 传输到卡使用脉宽T=3μs 的Miller 编码。
图：4 显示了环形天线的两维磁场右边是磁场的分布状态最高的场强在线圈的区域左边部分显示了距离是d 时场强H 的幅值标记的是根据ISO
14443 最小场强HMIN=1.5A/m 的线。
图4：环形天线无干扰的磁场分布
3.1天线的仿真
天线的电磁软件仿真是现代天线设计的必要辅助工具。它可以加快设计速度，减少修正周期。提前产品上市的时间。
图5：用CST建模的LH近耦合RFID天线的磁场电流分布
图6：设计完成后的PCB
二 软件设计
下面是PHILIPS公司的原码，仅供参考。使用时请尊重版权法
#ifndef MFRC500REG_H
#define MFRC500REG_H
#ifdef __cplusplus
extern "C"
{
#endif
// PAGE 0 Command and Status
#define
RegPage
0x00 //!< Page Select Register
#define
RegCommand
0x01 //!< Command Register
#define
RegFIFOData
0x02 //!< FiFo Register
#define
RegPrimaryStatus 0x03
//!< Modem State/IRQ/ERR/LoHiAlert Reg
#define
RegFIFOLength
0x04 //!< Buffer length Register
#define
RegSecondaryStatus 0x05 //!<
diverse status flags
#define
RegInterruptEn
0x06 //!< IRQ enable Register
#define
RegInterruptRq
0x07 //!< IRQ bits Register
// PAGE 1 Control and Status
#define
RegControl
0x09 //!< processor control
#define
RegErrorFlag
0x0A /*!< error flags showing the error
status of the last command executed */
#define
RegCollPos
0x0B /*!< bit position of the first bit
collision detected on the
RF-interface */
#define
RegTimerValue
0x0C //!< preload value of the timer
#define
RegCRCResultLSB
0x0D //!< LSB of the CRC Coprocessor register
#define
RegCRCResultMSB
0x0E //!< MSB of the CRC Coprocessor register
#define
RegBitFraming
0x0F //!< Adjustments for bit oriented frames
// PAGE 2 Transmitter and Coder
Control
#define
RegTxControl
0x11 //!< controls the logical behaviour of
//!< the antenna driver pins TX1 and TX2
#define
RegCwConductance 0x12
/*!< selects the conductance of the
antenna driver pins TX1 and TX2 */
#define
RFU13
0x13 //!< RFU
#define
RegCoderControl
0x14 //!< selects coder rate
#define
RegModWidth
0x15 /*!< selects the width of the
modulation pulse */
#define
RFU16
0x16 //!< RFU
#define
RFU17
0x17 //!< RFU
// PAGE 3 Receiver and Decoder
Control
#define
RegRxControl1
0x19 //!< controls receiver behaviour
#define
RegDecoderControl 0x1A //!<
controls decoder behaviour
#define
RegBitPhase
0x1B /*!< selets the bit phase between
transmitter and receiver clock */
#define
RegRxThreshold
0x1C /*!< selects thresholds for the bit
decoder */
#define
RFU1D
0x1D //!< RFU
#define
RegRxControl2
0x1E /*!< controls decoder behaviour and
defines the input source for the
receiver */
#define
RegClockQControl 0x1F
/*!< controls clock generation for the
90?phase shifted Q-channel clock */
// PAGE 4 RF-Timing and Channel
Redundancy
#define
RegRxWait
0x21 /*!< selects the time interval after
transmission, before receiver starts */
#define RegChannelRedundancy
0x22 /*!< selects the kind and mode of
checking the data integrity on the
RF-channel */
#define
RegCRCPresetLSB
0x23 /*!< LSB of the pre-set value for the
CRC register */
#define
RegCRCPresetMSB
0x24 /*!< MSB of the pre-set value for the
CRC register */
#define
RFU25
0x25 //!< RFU
#define
RegMfOutSelect
0x26 /*!< selects internal signal applied to
pin MfOut */
#define
RFU27
0x27 //!< RFU
// PAGE 5 FIFO, Timer and IRQ-Pin
Configuration
#define
RegFIFOLevel
0x29 /*!< Defines level for FIFO over- and
underflow warning */
#define
RegTimerClock
0x2A //!< selects the divider for the timer clock
#define
RegTimerControl
0x2B /*!< selects start and stop conditions
for the timer */
#define
RegTimerReload
0x2C /*!< defines the pre-set value for the
timer */
#define
RegIRqPinConfig
0x2D /*!< configures the output stage of
pin IRq */
#define
RFU2E
0x2E //!< RFU
#define
RFU2F
0x2F //!< RFU
// PAGE 6 RFU
#define
RFU31
0x31 //!< RFU
#define
RFU32
0x32 //!< RFU
#define
RFU33
0x33 //!< RFU
#define
RFU34
0x34 //!< RFU
#define
RFU35
0x35 //!< RFU
#define
RFU36
0x36 //!< RFU
#define
RFU37
0x37 //!< RFU
// PAGE 7 Test Control
#define
RFU39
0x39 //!< RFU
#define
RegTestAnaSelect 0x3A
//!< selects analog test mode
#define
RFU3B
0x3B //!< RFU
#define
RFU3C
0x3C //!< RFU
#define
RegTestDigiSelect 0x3D //!<
selects digital test mode
#define
RFU3E
0x3E //!< RFU
#define
RegTestDigiAccess 0x3F
#define DEF_FIFO_LENGTH 64 //!<
default FIFO size
//
P C D - C O M M A N D S
#define
PCD_IDLE
0x00 /*!< No action: cancel current command
or home state */
#define PCD_WRITEE2 0x01
//!< Get data from FIFO and write it to the E2PROM
#define PCD_READE2
0x03 /*!< Read data from E2PROM and put it into the
FIFO */
#define PCD_LOADCONFIG 0x07 /*!< Read
data from E2PROM and initialise the
registers */
#define PCD_LOADKEYE2 0x0B /*!<
Read a master key from the E2PROM and put
it into the master key buffer */
#define PCD_AUTHENT1 0x0C
/*!< Perform the first part of the card
authentication using the Crypto1 algorithm.
Remark: The master key is automatically taken
from the master key buffer. this implies,
that the command LoadKeyE2 has to be executed
before using a certain key for card
authentication */
#define PCD_CALCCRC 0x12
/*!< Activate the CRC-Coprocessor
Remark: The result of the CRC calculation can
be read from the register CRCResultXXX */
#define PCD_AUTHENT2 0x14
/*!< Perform the second part of the card
authentication using the Crypto1 algorithm. */
#define PCD_RECEIVE 0x16
/*!< Activate Receiver Circuitry. Before the
receiver actually starts, the state machine
waits until the time configured in the
register RxWait has passed.
Remark: It is possible to read any received
data from the FIFO while the Receive command
is active. Thus it is possible to receive an
unlimited number of bytes by reading them
from the FIFO in timer. */
#define PCD_LOADKEY 0x19
/*!< Read a master key from the FIFO and put it
into the master key buffer
Remark: The master key has to be prepared in
a certain format. Thus, 12 byte have to be
passed to load a 6 byte master key */
#define PCD_TRANSMIT 0x1A
/*!< Transmit data from FIFO to the card
Remark: If data is already in the FIFO when
the command is activated, this data is
transmitted immediately. It is possible to
write data to the FIFO while the Transmit
command is active. Thus it is possible to
transmit an unlimited number of bytes in one
stream by writting them to the FIFO in time.*/
#define PCD_TRANSCEIVE 0x1E /*!<
Transmits data from FIFO to the card and
after that automatically activates the
receiver. Before the receiver actually
starts,the state machine waits until the
time configured in the register RxWait has
passed.
Remark: This command is the combination of
Transmit and Receive.*/
#define PCD_RESETPHASE 0x3F /*!< Runs
the Reset- and Initialisation Phase
Remark: This command can not be activated by
software, but only by a Power-On or
Hard Reset */
#ifdef __cplusplus
}
#endif
#endif //MFRC500REG_H
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