Cadence和ARM周三宣布ARM11
MPCore的多核处理和ARM1176JZF-S的低功耗实现两项参考方法，此举将对基于ARM的用户产品性能提高大有裨益。
新闻要点：
ARM，Cadence联合发布多核、低功耗参考设计方法，分别针对ARM11 MPCore和ARM1176JZF-S。
ARM11 MPCore支持ARM的MPCore多处理技术。
ARM1176JZF-S
的低功耗方法支持IEM技术（能降低60%的CPU能耗，支持动态电压和频率缩放硬件技术）和常规功率格式(CPF)。
新方法经验将应用到最新Cortex A9处理器和ARM Cortex-A9 MPCore多核处理器上。
该设计方法投入应用计划于2008年上半年，来迎合处理器的生产发布。
ARM, Cadence create multicore, low-power device methodologies
By Ann Steffora Mutschler, Senior Editor -- Electronic News,
12/6/2007
To provide enhanced design solutions to mutual customers designing multicore, low-power devices, Cadence Design Systems Inc. and ARM announced Wednesday two implementation reference methodologies developed by the companies -- one for the ARM11 MPCore multicore processor and the other for low-power implementation of the ARM1176JZF-S processor.
The ARM11 MPCore multicore processor contains ARM’s MPCore multiprocessing technology, which is meant to allow scalability for performance and power management that can address the requirements of multiple designs.
ARM also noted that both the ARM11 MPCore processor and low-power ARM1176JZF-S processor flows have been pre-validated with ARM Artisan physical IP in order to optimize the implementation of ARM synthesizable processor IP.
The low-power reference methodology for the ARM1176JZF-S processor was designed to support IEM technology, which has been shown to reduce CPU energy consumption by more than 60 percent, and supports the dynamic voltage and frequency scaling (DVFS) hardware technique that IEM technology exploits, ARM noted.
Further, the reference methodologies comprehend the Common Power Format (CPF), which allows the up-front specification of power domains, power modes, level shifting and isolation rules to automate advanced low-power design techniques, as well as leverage Cadence’s low-power software tools including the SoC Encounter RTL-to-GDSII system, Encounter RTL Compiler with global synthesis, Encounter Conformal Low Power, and VoltageStorm power rail analysis.
ARM and Cadence said they would leverage their experience gained in developing these advanced flows for low-power and multiprocessing applications in the development of new reference methodologies for the latest ARM processors, the Cortex A9 processor and the ARM Cortex-A9 MPCore multicore processor.
User Ying F. Chang, engineering director for custom SOC solutions engineering at NEC Electronics America said with the Cadence low-power solution, which includes Encounter RTL Compiler and SoC Encounter GXL, NEC has been able to exceed performance goals for its ARM processor-based ASIC design efforts.
The reference methodologies are planned to be available in the first half of 2008, to coincide with the production release of the processors.
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