freewind的博客

statem.v

module statem(clk, in, reset, out);

input clk, in, reset;
output [3:0] out;

reg [3:0] out;
reg [1:0] state;

parameter zero=0, one=1, two=2, three=3;

always @(state)
     begin
        
               zero:
                    out = 4'b0000;
               one:
                    out = 4'b0001;
               two:
                    out = 4'b0010;
               three:
                    out = 4'b0100;
               default:
                    out = 4'b0000;
          endcase
     end

always @(posedge clk or posedge reset)
     begin
          if (reset)
               state = zero;
          else
               case (state)
                    zero:
                         state = one;
                    one:
                         if (in)
                              state = zero;
                         else
                              state = two;
                    two:
                         state = three;
                    three:
                         state = zero;
               endcase
     end

endmodule





module mux(EN ,IN0 ,IN1 ,IN2 ,IN3 ,SEL ,OUT );

input  EN ;
input  [7:0] IN0 ,IN1 ,IN2 ,IN3 ;
input  [1:0] SEL ;

output [7:0] OUT ;
reg  [7:0] OUT ;


always @(SEL  or EN  or IN0  or IN1  or IN2  or IN3 )
begin
if (EN  == 0) OUT  = {8{1'b0}};
else
case (SEL )
0 : OUT  = IN0 ;
1 : OUT  = IN1 ;
2 : OUT  = IN2 ;
3 : OUT  = IN3 ;
default : OUT  = {8{1'b0}};
   endcase
end

endmodule