Lab6 – HW/SW System Debug
PowerPC Processor
HW/SW System Debug Lab: PowerPC
Introduction
This lab guides you through the process of debugging the processor system. XPS and ChipScope will be used to have visibility into both the Hardware and Software of the system.
Objectives
After completing this lab, you will be able to:
• Add ChipScope Analyzers into a system
• Cross debug with Chipscope Analayzer and the SDK debugger
Procedure
This lab comprises several steps involving simulation. Below each general instruction for a given procedure, you will find accompanying step-by-step directions and illustrated figures providing more detail for performing the general instruction. If you feel confident about a specific instruction, feel free to skip the step-by-step directions and move on to the next general instruction in the procedure.
Opening the Project Step 1
General Flow for this Lab:
Create a lab6 folder under c:\xup\embedded\ppc\labs\. If you wish to continue with your completed design from lab5 then copy the contents of the lab5 folder into the lab6 folder. Launch Xilinx Platform Studio (XPS) and open the project file located in c:\xup\embedded\xupv2pro\labs\lab6.
Create a lab6 folder in the c:\xup\embedded\xupv2pro\labs directory. If you wish to continue with your completed design from lab5 then copy the contents of the lab5 folder into the lab6 folder.
Open XPS by clicking Start Programs Xilinx Platform Studio 8.1i Xilinx Platform Studio
Select Open Recent Project, Click OK and browse to C:\xup\embedded\xupv2pro\labs\lab6
Click system.xmp to open the project
ChipScope Core Instantiation Step 2
Add the ChipScope cores from the IP Catalog to the design. Configure the device and the design to the following ports, as shown in the figure 6-2. Setup the trigger to trigger when a certain values are on the OPB address, OPB data, and OPB control bus.
Figure 6-2. ChipScope Core Connections
Add the chipscope_icon and chipscope_opb_iba peripherals from the Debug section of the IP Catalog and connect the chipscope_opb_iba to the OPB Bus
Figure 6-3. Chipscope OPB Bus connections
In the Ports tab, connect the chipscope_cores and ppc405_0 as shown in the following table
Double-click on the chipscope_icon_0 IP instance and set the Number of Control Ports to the value of 1
Double-click the chipscope_opb_iba_0 IP instance from the right hand side and set the following parameters according to the figures below, leaving the rest default:
Select Download to generate the new HW system and link in the SW. Operation should still be the same
SDK and ChipScope Operation Step 3
Open an SDK project and establish a connection to the target using XMD. Having successfully generated your design it is possible to begin viewing it in operation using the SDK debugger and ChipScope Pro tools.
Starting the SDK debugger (Software Debug)
Launch SDK: select Software Launch Platform Studio SDK
Click cancel when the wizard opens
Delete the existing sdk_lab project that was created in lab 5 (right-click on sdk_lab and select delete – do not delete contents)
Import the lab6 SDK project: File Import Existing Project Into Workspace
Click <Next>, browse to the following directory: \lab6\SDK_projects\sdk_lab and then click <Finish>
Figure 6-4. SDK Project
Setup the target connection by going to Run Run…
Figure 6-5. Specify Project and .elf Location
Click the Run button
The software code will be downloaded to the board.
Click the debug sdk_lab button
The SDK Debugger should now be connected to the target as illustrated in the Figure below
Figure 6-6. SDK Debugger Connected to Target via XMD
Code operation will be halted at the first line following the main( ) routine.
Highlight the Thread [0] line and select Resume and note the LEDs flashing indicating proper system operation.
Click on 
to suspend the program
Starting ChipScope Pro (Hardware Debug)
Launch the ChipScope Pro Analyzer tool from the program group or desktop icon.
Click on the Open Cable/Search JTAG chain icon
This will identify the devices on the JTAG chain. Click OK to open ChipScope Pro Analyzer with default Trigger Setup and Waveform signal windows.
Figure 6-7. ChipScope JTAG Device Order
Select File Import. In the Signal Import dialogue click on the Select New File button.
Browse to the XPS design directory and the select the following file c:\xup\embedded\labs\lab6\implementation\chipscope_opb_iba_0_wrapper\ chipscope_opb_iba_0.cdc and click OK as shown in Figure 6-8
Figure 6-8. ChipScope Signal Import
The signals associated with the OPB core should be listed in the Trigger Setup and Waveform signal windows.
HW/SW Debug Interaction Step 4
Trigger/Waveform SetUp Windows
Figure 6-9. ChipScope Waveform Windows
Set M0:TRG0:OPB_CTRL OPB_RNW bit == 0 by clicking the + sign under M0 and selecting the OPB_RNW bit and changing its value to 0 under Value field
Change the Radix of M1and M2 from binary (Bin) to Hexadecimal (Hex) by clicking on the respective boxes and selecting Hex
Set M1:TRIG1:OPB_ABUS == 7D80_0000 (or base address of LEDs_8Bit peripheral) and M2:TRIG2:OPB_DBUS == 0000_0005 by selecting and adjusting the value box
Adjust the Trigger Condition Equation by selecting the box in the TriggerCondition0 dialogue box that appears. Select M0 and Select M1 and Select M2. The Trigger Condition
Equation should now display M0 && M1 && M2. Click OK.
Set the trigger window depth to 512 and position to 0
Delete all the signals from the Waveform window using [Shift Select]. In the Signals window, select OPB_Dbus, Right click on it and select Add To View and then select Waveform. The signal will be added in the Waveform window. Do the same for
OPB_ABUS and OPB_RNW.
Set up the Output Enable of the Trigger to Pulse (High). This will cross trigger the debugger. Setup the trigger by selecting Trigger Setup -> Run as shown below
Run Software debugger and wait for the condition to trigger
In software debugger window (opened before) click on Resume to continue with debug.
The hardware should trigger and then this will cross trigger the SW asynchronous stop in GDB. Basic ChipScope Pro Trigger settings along with simple waveforms are established. You should see results in Chipscope-Pro similar to that of figure 6-10 below
Figure 6-10. Chipscope-Pro Debug Results
Note: You may have to zoom in using the X/O cursors to see the results. Refer to v8.2 Chipscope Users Manual, provided in the /docs directory, for more information.
Conclusion
Chipscope HW debug modules can be added as IP modules in EDK, and the ChipScope analyzer can be used in conjunction with SDK debugger, to provide a debug environment that allows cross triggering and debug between hardware and software using a shared JTAG connection.
Completed MHS File
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 8.2 Build EDK_Im.14
# Tue Aug 29 14:15:28 2006
# Target Board: Xilinx XUP Virtex-II Pro Development System Rev C
# Family: virtex2p
# Device: xc2vp30
# Package: ff896
# Speed Grade: -7
# Processor: PPC 405
# Processor clock frequency: 300.000000 MHz
# Bus clock frequency: 100.000000 MHz
# Debug interface: FPGA JTAG
# On Chip Memory : 64 KB
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
PORT dip = DIP, DIR = I, VEC = [0:3]
PORT push = PUSH, DIR = I, VEC = [0:4]
PORT led = fpga_0_LEDs_4Bit_GPIO_d_out, DIR = O, VEC = [0:3]
BEGIN ppc405
PARAMETER INSTANCE = ppc405_0
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_0
BUS_INTERFACE IPLB = plb
BUS_INTERFACE DPLB = plb
PORT PLBCLK = sys_clk_s
PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
PORT RSTC405RESETCHIP = RSTC405RESETCHIP
PORT RSTC405RESETCORE = RSTC405RESETCORE
PORT RSTC405RESETSYS = RSTC405RESETSYS
PORT CPMC405CLOCK = proc_clk_s
PORT EICC405EXTINPUTIRQ = interrupt
PORT DBGC405UNCONDDEBUGEVENT = dbg_stop
END
BEGIN ppc405
PARAMETER INSTANCE = ppc405_1
PARAMETER HW_VER = 2.00.c
BUS_INTERFACE JTAGPPC = jtagppc_0_1
END
BEGIN jtagppc_cntlr
PARAMETER INSTANCE = jtagppc_0
PARAMETER HW_VER = 2.00.a
BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
BUS_INTERFACE JTAGPPC1 = jtagppc_0_1
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = reset_block
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Ext_Reset_In = sys_rst_s
PORT Slowest_sync_clk = sys_clk_s
PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
PORT Core_Reset_Req = C405RSTCORERESETREQ
PORT System_Reset_Req = C405RSTSYSRESETREQ
PORT Rstc405resetchip = RSTC405RESETCHIP
PORT Rstc405resetcore = RSTC405RESETCORE
PORT Rstc405resetsys = RSTC405RESETSYS
PORT Bus_Struct_Reset = sys_bus_reset
PORT Dcm_locked = dcm_0_lock
END
BEGIN plb_v34
PARAMETER INSTANCE = plb
PARAMETER HW_VER = 1.02.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT PLB_Clk = sys_clk_s
END
BEGIN opb_v20
PARAMETER INSTANCE = opb
PARAMETER HW_VER = 1.10.c
PARAMETER C_EXT_RESET_HIGH = 1
PORT SYS_Rst = sys_bus_reset
PORT OPB_Clk = sys_clk_s
END
BEGIN plb2opb_bridge
PARAMETER INSTANCE = plb2opb
PARAMETER HW_VER = 1.01.a
PARAMETER C_DCR_INTFCE = 0
PARAMETER C_RNG0_BASEADDR = 0x40000000
PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
PARAMETER C_NUM_ADDR_RNG = 1
BUS_INTERFACE SPLB = plb
BUS_INTERFACE MOPB = opb
END
BEGIN opb_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_CLK_FREQ = 100000000
PARAMETER C_BASEADDR = 0x40600000
PARAMETER C_HIGHADDR = 0x4060ffff
BUS_INTERFACE SOPB = opb
PORT RX = fpga_0_RS232_Uart_1_RX
PORT TX = fpga_0_RS232_Uart_1_TX
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_1
PARAMETER HW_VER = 1.00.b
PARAMETER c_plb_clk_period_ps = 10000
PARAMETER c_baseaddr = 0xffff0000
PARAMETER c_highaddr = 0xffffffff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_PORTA
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_PORTA
END
BEGIN dcm_module
PARAMETER INSTANCE = dcm_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLK0_BUF = TRUE
PARAMETER C_CLKFX_BUF = TRUE
PARAMETER C_CLKFX_DIVIDE = 1
PARAMETER C_CLKFX_MULTIPLY = 3
PARAMETER C_CLKIN_PERIOD = 10.000000
PARAMETER C_CLK_FEEDBACK = 1X
PARAMETER C_DFS_FREQUENCY_MODE = HIGH
PARAMETER C_DLL_FREQUENCY_MODE = LOW
PARAMETER C_EXT_RESET_HIGH = 1
PORT CLKIN = dcm_clk_s
PORT CLK0 = sys_clk_s
PORT CLKFX = proc_clk_s
PORT CLKFB = sys_clk_s
PORT RST = net_gnd
PORT LOCKED = dcm_0_lock
END
BEGIN plb_bram_if_cntlr
PARAMETER INSTANCE = plb_bram_if_cntlr_2
PARAMETER HW_VER = 1.00.b
PARAMETER c_baseaddr = 0x00000000
PARAMETER c_highaddr = 0x00003fff
BUS_INTERFACE SPLB = plb
BUS_INTERFACE PORTA = plb_bram_if_cntlr_2_PORTA
END
BEGIN bram_block
PARAMETER INSTANCE = plb_bram_if_cntlr_2_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = plb_bram_if_cntlr_2_PORTA
END
BEGIN opb_gpio
PARAMETER INSTANCE = dip1
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40020000
PARAMETER C_HIGHADDR = 0x400201FF
BUS_INTERFACE SOPB = opb
PORT GPIO_in = DIP
END
BEGIN opb_gpio
PARAMETER INSTANCE = push1
PARAMETER HW_VER = 3.01.b
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_IS_BIDIR = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x40000000
PARAMETER C_HIGHADDR = 0x400001FF
BUS_INTERFACE SOPB = opb
PORT GPIO_in = PUSH
END
BEGIN my_led
PARAMETER INSTANCE = my_led_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x7d800000
PARAMETER C_HIGHADDR = 0x7d8001ff
BUS_INTERFACE SOPB = opb
PORT LED = fpga_0_LEDs_4Bit_GPIO_d_out
END
BEGIN opb_timer
PARAMETER INSTANCE = delay
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x41C00000
PARAMETER C_HIGHADDR = 0x41C001FF
PARAMETER C_ONE_TIMER_ONLY = 1
BUS_INTERFACE SOPB = opb
PORT Interrupt = timer1
PORT CaptureTrig0 = net_gnd
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x412001FF
BUS_INTERFACE SOPB = opb
PORT Intr = timer1
PORT Irq = interrupt
END
BEGIN chipscope_icon
PARAMETER INSTANCE = chipscope_icon_0
PARAMETER HW_VER = 1.01.a
PORT control0 = chipscope_icon_0_control0
END
BEGIN chipscope_opb_iba
PARAMETER INSTANCE = chipscope_opb_iba_0
PARAMETER HW_VER = 1.01.a
PARAMETER C_CONTROL_UNIT_MATCH_TYPE = extended with edges
PARAMETER C_DATA_UNIT_MATCH_TYPE = extended with edges
PARAMETER C_ENABLE_TRIGGER_SEQUENCER = 0
PARAMETER C_ENABLE_STORAGE_QUALIFICATION = 0
BUS_INTERFACE MON_OPB = opb
PORT chipscope_icon_control = chipscope_icon_0_control0
PORT iba_trig_out = dbg_stop
END
<完>
