一种集成电路，属于PLD，电路规模较大。
CPLD是指结构比较复杂的可编程逻辑器件，它包括下述输出宏单元结构：
- 可编程I/O 允许用户对这些引脚编程，作为输入或输出。
- 寄存器输出和反馈 可用于实现计数器和移位寄存器等。
- 异或门输出结构，可用于一般用户多功能计数，能十分有效地建立大的计数器。
AMD公司最先生产带有宏单元的可编程逻辑器件PAL22V10。目前PAL22V10已成为划分PLD的界限。可编程逻辑器件所包含的门数大于PAL22V10所包含则门数，就被认为是复杂可编程逻辑器件，即CPLD。
可以认为CPLD基本上是原来的可编程逻辑器件的扩展。它常常由可编程逻辑的功能块围绕一个位于中心、时延固定可编程互连矩阵构成。由于用固定长度的金属线实现逻辑单元之间的互连，而可编程逻辑单元又是类似PAL的与阵列，使得CPLD与FPGA相比较很容易计算输人到输出的传输延迟，显然也会有一些灵活性的限制。但是，CPLD的设计比FPGA简单。
虽然CPLD的结构一般都很相似，而且一般认为CPLD都有100％的布通率，但是由于可编得互连矩阵的结构不同，实际上也会有差别。
CPLD 是 Complex PLD 的简称，顾名思义，其是一种较 PLD 为复杂的逻辑元件。
CPLD 是一种整合性较高的逻辑元件。由于具有高整合性的特点，故其有性能提升，可靠度增加， PCB 面积减少及成本下降等优点。 CPLD 元件，基本上是由许多个逻辑方块（ Logic Blocks ）所组合而成的。而各个逻辑方块均相似于一个简单的 PLD 元件（如 22V10 ）。逻辑方块间的相互关系则由可变成的连线架构，将整个逻辑电路合成而成。
常见的 CPLD 元件有 Altera 公司的 Max5000 及 Max7000 系列。 Cypress 的 Max340 及 Flash370 系列等，一般来说 CPLD 元件的gate count约在 1000~7000 Gate 之间。
A complex programmable logic device (CPLD) is a programmable logic device with complexity between that of PALs and FPGAs, and architectural features of both. The building block of a CPLD is the macro cell, which contains logic implementing disjunctive normal form expressions and more specialized logic operations.
Features in common with PALs:
- Non-volatile configuration memory. Unlike many FPGAs, an external configuration ROM isn't required, and the CPLD can function immediately on system start-up.
- For many legacy CPLD devices, routing constrains most logic blocks to have input and output signals connected to external pins, reducing opportunities for internal state storage and deeply layered logic. This is usually not a factor for larger CPLDs and newer CPLD product families.
Features in common with FPGAs:
- Large number of gates available. CPLDs typically have the equivalent of thousands to tens of thousands of logic gates, allowing implementation of moderately complicated data processing devices. PALs typically have a few hundred gate equivalents at most, while FPGAs typically range from tens of thousands to several million.
- Some provisions for logic more flexible than sum-of-product expressions, including complicated feedback paths between macro cells, and specialized logic for implementing various commonly-used functions, such as integer arithmetic.
The most noticeable difference between a large CPLD and a small FPGA is the presence of on-chip non-volatile memory in the CPLD. This distinction is rapidly becoming less relevant, as several of the latest FPGA products also offer models with embedded configuration memory.
The characteristic of non-volatility makes the CPLD the device of choice in modern digital designs to perform 'boot loader' functions before handing over control to other devices not having this capability. A good example is where a CPLD is used to load configuration data for an FPGA from non-volatile memory.
CPLDs were an evolutionary step from even smaller devices that preceded them, PLAs (first shipped by Signetics), and PALs. These in turn were preceded by standard logic products, that offered no programmability and were "programmed" by wiring several standard logic chips together.
As CPLDs and FPGAs become more advanced the differences between the two device types will continue to blur. While this trend may appear to make the two types more difficult to keep apart, the architectural advantage of CPLDs combining low cost, non-volatile configuration, and macro cells with predictable timing characteristics will likely be sufficient to maintain a product differentiation for the foreseeable future.[citation needed]
See also
- Erasable programmable logic device (EPLD)
- Simple programmable logic device (SPLD)
- Macrocell array
- Programmable array logic (PAL)
- Programmable logic device (PLD)
- Field-programmable gate array (FPGA)
- VHSIC Hardware Description Language (VHDL)
- Verilog Hardware Description Language
友情链接：
