openhw_llh的博客

继续上面的文章。这个是下层的主要模块；里面已例化两块1M的分布式ram；

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version : 9.1i
//  \   \         Application : sch2verilog
//  /   /         Filename : usrt_sch.vf
// /___/   /\     Timestamp : 08/25/2008 17:18:53
// \   \  /  \
//  \___\/\___\
//
//Command: "D:\Program Files\xilinx ise9.1\bin\nt\sch2verilog.exe" -intstyle ise -family spartan3e -w "D:/Program Files/project lib/uart_test31/usrt_sch.sch" usrt_sch.vf
//Design Name: usrt_sch
//Device: spartan3e
//Purpose:
//    This verilog netlist is translated from an ECS schematic.It can be
//    synthesized and simulated, but it should not be modified.
//
`timescale 1ns / 1ps

module usrt_sch(addram1_rd,
                addram2_wr,
                clk,
                dinaram2,
                en_ram1_rd,
                reset,
                reset_n,
                rxd,
                send,
                wea_ram2,
                dout_ram1,
                error,
                txd);

    input [9:0] addram1_rd;
    input [9:0] addram2_wr;
    input clk;
    input [7:0] dinaram2;
    input en_ram1_rd;
    input reset;
    input reset_n;
    input rxd;
    input send;
    input [0:0] wea_ram2;
   output [7:0] dout_ram1;
   output error;
   output txd;
  
   wire [0:0] XLXN_25;
   wire XLXN_26;
   wire [9:0] XLXN_55;
   wire XLXN_56;
   wire XLXN_57;
   wire [7:0] XLXN_60;
   wire [9:0] XLXN_61;
   wire [7:0] XLXN_62;
   wire [7:0] XLXN_64;
  
   uart_top XLXI_2 (.clk(clk),
                    .reset_n(reset_n),
                    .RxD(rxd),
                    .send(send),
                    .send_bus(XLXN_64[7:0]),
                    .error(error),
                    .recv(XLXN_26),
                    .recv_bus(XLXN_60[7:0]),
                    .send_over(XLXN_56),
                    .TxD(txd));
   control XLXI_3 (.nrst(reset),
                   .test(XLXN_26),
                   .addr_out(XLXN_61[9:0]));
   NAND2 XLXI_7 (.I0(send),
                 .I1(send),
                 .O(XLXN_25[0]));
   control XLXI_16 (.nrst(reset),
                    .test(XLXN_57),
                    .addr_out(XLXN_55[9:0]));
   FD XLXI_17 (.C(clk),
               .D(XLXN_56),
               .Q(XLXN_57));
   defparam XLXI_17.INIT = 1'b0;
   con_ml XLXI_19 (.clk(clk),
                   .din(XLXN_60[7:0]),
                   .dout(XLXN_62[7:0]));
   dram_top XLXI_20 (.addra(XLXN_61[9:0]),
                     .addrb(addram1_rd[9:0]),
                     .clka(clk),
                     .clkb(clk),
                     .dina(XLXN_62[7:0]),
                     .enb(en_ram1_rd),
                     .wea(XLXN_25[0]),
                     .doutb(dout_ram1[7:0]));
   dram_top XLXI_21 (.addra(addram2_wr[9:0]),
                     .addrb(XLXN_55[9:0]),
                     .clka(clk),
                     .clkb(clk),
                     .dina(dinaram2[7:0]),
                     .enb(send),
                     .wea(wea_ram2[0]),
                     .doutb(XLXN_64[7:0]));
endmodule