AutoPilot, a powerful ESL synthesis software tool,
automatically generates efficient RTL code from C, C++, or SystemC descriptions and simultaneously optimizes logic, interconnects,
performance, and power, providing superior platform-based
system-level synthesis capability. The behavioral design descriptions are parsed and optimized by
AutoESL’s enhancements to a fully GNU compatible compiler.
AutoPilot’s core technology is an advanced ESL synthesis and optimization engine that manages large systems described in a high-level language with
minimal modifications to its source code. AutoPilot’s
synthesis engine performs precise platform pre-characterization that enables more informed optimizations. The
characterization libraries contain delay, area and power information for resources such as ALUs, multipliers, memories, and steering logic. Layout information of the target FPGA is also utilized by the
physical-aware synthesis engine. Constraints for the RTL
code such as multi-cycle and false paths are automatically
generated to insure design closure.
How is parallelization achieved? （怎样完成从串行程序设计语言到并行程序设计语言的转换？）
- Parallelization is extracted from the algorithm by examining the
untimed system-level behavioral source code and using a GNU-compatible software compiler to apply advanced code transformation, optimization techniques
such as loop unrolling, if-conversion, loop flattening and data dependence analysis（???).
使用GNU编译工具，实现代码优化
- The compiler automatically employs behavior-level scheduling and
resource binding on data-intensive and control-intensive algorithms
that can include large memory structures
- The designer can also specify course-grain(???) parallelism using SystemC
Level of Abstraction — How different is it from coding in HDL?
- With AutoPilot, software written in C/C++/SystemC-code used at the
system level does not have to be re-written for synthesis
- Source code is written at the behavioral level versus at an RTL
level
- Throughput, latency and various pipeline options can be specified
in a constraint file used by the synthesis engine versus explicit
coding of timing and concurrency in RTL
- Design of a large system is driven by behavioral- and
architectural-level executable models written in C/C++/SystemC
instead of hardware-specific HDL models
- Much more efficient and faster evaluation of different
micro-architectures, hardware and software boundaries using a
high-level language
- 10:1 reduction in code base size using a high-level language versus
HDL
Skill pre-requisite ?
- No knowledge of FPGA and hardware design is necessary but is
helpful
- AutoPilot can be used by both software and hardware designers
familiar with high -level languages such as C, C++, SystemC, or
M-code
- Working knowledge of software centric compilation and debugging
environments such as the industry standard Eclipse CDT and/or
GNU/make
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