Designing 2D and 3D Network-on-Chip Architectures-(2014)

Moore’s law continues unabated and new design challenges lead to new design methodologies and even paradigm shifts. One such recent development is the introduction of three-dimensional integration technology. Efficiently utilizing novel technologies poses new design challenges and therefore require new design methodologies and EDA tools. Training engineers in these methodologies and design techniques is essentially done at the graduate level and once these technologies become the established paradigm, at the undergraduate level.

Network-on-Chip technology has been a popular research topic for a while now, and is the current design paradigm for multi- and many-core architectures. It is also a natural complement for 3D integration technology. Its multifaceted and multidisciplinary nature imposes a number of challenges both in the industrial and academic environments. While at the graduate level it is common or even preferable to use papers, case studies and assignments as the main teaching tools, at the undergraduate level a suitable textbook is indispensable. Since there is an increased need to include an introduction to Networks-on-Chip in undergraduate curricula, such a textbook is required, and has been missing from the literature for too long. At the same time, the large body of research work in the field must be also made available in an organized way for graduate students, researchers, and professionals to use as reference.