乒乓ram代码及仿真波形
[摘要]

moduletop

( inputclk, inputrst_n, input[15:0]in1, inputstart, inputends, outputreg[15:0]out );

wire[3:0]waddra;

wire [3:0]raddra;

wire[15:0]dataa;

wire[3:0]waddrb;

wire[3:0]raddrb;

wire ppang;

wire[15:0]data_out0;

wire[15:0]data_out1;

wirewr0;

wirewr1;

wirerd0;

wirerd1;

regrd0_d;

regrd1_d;

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上传时间:2019/04/15