免费学习ARM_M0 相关知识
[摘要]

来自于OPENCORE的Verilog语言的embedded_risc软核
SOC设计,包含比较多的内容。可以作为学习参考代码。比较有价值
顶层文件描述:
MODULE:  Top Level System On A Chip Design
FILE NAME: soc.v
DATE:  May 7th, 2002
AUTHOR:  Hossein Amidi
COMPANY:
CODE TYPE: Register Transfer Level
DESCRIPTION: This module is the top level RTL code of System On a Chip Verilog code.
It will instantiate the following blocks in the ASIC:
1)   Vertex STARTUP
2) DLL
3) RISC uProcessor
4) DMA Cntrl
5) LRU Data Cache
6) LRU Instruction Cache
7) Bus Arbiter
8) UART
9) Timer
10)  Flash Controller
11) SDRAM Controlle

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上传时间:2019/04/24