Unlike traditional wafer-level packaging, glass-based panel-level packaging relies on large-format square substrates to achieve a dual leap in capacity and utilization. However, challenges such as process control for large substrates, precision defect detection, and heterogeneous material adaptation constrain its scaled implementation. Recently, Applied Materials discussed the current bottlenecks and solutions for large-format panel packaging with reporters from China Electronics News.
Currently, AI and high-performance computing (HPC) chips are rapidly upgrading towards high integration, high density, and heterogeneity. The shortcomings of traditional wafer packaging are becoming increasingly prominent, with size limitations, low output efficiency, and persistently high unit costs making it increasingly difficult to meet the scaled mass production demands of computing chips. Panel-level packaging technology, characterized by "large format, high utilization, high capacity, and low cost," has become a crucial alternative route for the iteration of advanced packaging.
Compared to traditional wafer-level packaging, a core innovation of panel-level packaging is "changing round to square," replacing circular silicon wafers with square glass substrates, which significantly increases the effective utilization area of the substrate.
Industry research shows that for large-format interposer applications, panel-level packaging is expected to increase area utilization from approximately 45% for traditional 300mm wafers to 81%, bringing significant room for cost optimization. As AI and high-performance computing (HPC) demands continue to grow, panel-level packaging is becoming a key development direction in the advanced packaging field.
Liao Yujun, Vice President and General Manager of the Core Product Division, Display and Flexible Business Group at Applied Materials, told reporters from China Electronics News that current terminal chips impose comprehensive requirements on packaging, including large format, complexity, and low cost. Panel-level packaging is a critical technical path to adapt to this industry trend. Large-format substrates can not only support scaled mass production and amortize unit manufacturing costs but also accommodate the future development needs of high-density heterogeneous integration.
Although the technological advantages of panel-level packaging are clear, shifting from circular wafers to large-format glass-based panels is by no means a simple shape replacement, but a reconstruction of the entire manufacturing system. The feasibility of a technical solution does not equal the economic feasibility of mass production, and multiple practical bottlenecks still stand in the way of scaled commercialization.
Liao Yujun stated that the process challenges of glass-based panel-level packaging are highly concentrated. Large-format glass substrates impose stringent requirements on handling precision, process uniformity across the entire substrate, and precision alignment control. The process consistency of the entire panel directly determines the final yield. Meanwhile, as the feature sizes of redistribution layers (RDL) and interconnect structures continue to shrink, the precision ceiling of traditional packaging processes is gradually emerging, making it difficult to match the iteration pace of high-density packaging.
"Furthermore, the inherent material properties of glass further amplify process risks," Sun Yunhai, General Manager of Greater China, Display Business Group at Applied Materials, added to reporters from China Electronics News. Glass is highly brittle, and there are significant differences in the coefficient of thermal expansion (CTE) among glass, organic films, and copper wiring. During the manufacturing of through glass vias (TGV), micro-cracks and film delamination are highly prone to occur. Especially when the aspect ratio of the vias reaches 10:1 or above, the contradiction of insufficient adhesion between organic materials and the glass surface will be further exacerbated, threatening the long-term reliability of packaged devices. More challenging is that some subtle hidden defects cannot be promptly captured by conventional microscopic equipment and are often only exposed during backend terminal testing, which prolongs the R&D cycle, raises trial-and-error costs, and delays the yield ramp-up progress.
In summary, to achieve the leap to industrialization, panel-level packaging must overcome three core thresholds: process stability, defect detection sensitivity, and heterogeneous material adaptability.
Addressing the practical pain points of glass-based panel-level packaging, Applied Materials positions itself to focus on two key areas: inspection and metrology, and thin film deposition, creating a comprehensive solution tailored for large-substrate scenarios.
In the defect inspection and precision metrology segment, the resolution of traditional optical inspection can no longer keep up with the defect identification requirements of miniaturized packaging. Liao Yujun introduced that electron beam (eBeam) inspection equipment offers nanometer-level resolution, capable of identifying morphological defects as well as locating electrical failures such as short circuits and open circuits. It can penetrate multi-layer interconnect structures to analyze the root cause of issues, reduce false alarms, and shorten the process iteration cycle. Considering that eBeam inspection takes longer to process a single substrate, industry practice tends to adopt a combined mode of "high-speed wide-area optical screening + high-precision deep eBeam analysis" to balance mass production speed and yield control. The accompanying non-contact eBeam metrology abandons traditional probe contact methods, avoiding physical damage to fine devices and adapting to the trend of continuously shrinking chip sizes. Thin film deposition is playing a key role in addressing TGV process pain points. It is reported that chemical vapor deposition (CVD) technology can improve the bonding strength of organic materials on the glass surface, buffer the thermal stress mismatch among glass, copper wiring, and organic materials, reduce the risk of cracks and delamination, enhance film adhesion and overall process stability, and support high-aspect-ratio, high-density TGV designs. Liao Yujun stated that this set of technologies is already ready to collaborate with domestic panel manufacturers for process validation.
To further complete its product portfolio, in May 2026, Applied Materials announced an agreement to acquire the NEXX business of ASMPT, incorporating panel-level electrochemical deposition (ECD) technology to fill the critical gap in copper redistribution layer (RDL) electroplating. This forms a relatively complete equipment matrix covering physical vapor deposition (PVD), chemical vapor deposition (CVD), and electrochemical deposition (ECD), further improving the company's equipment portfolio in the field of panel-level advanced packaging and enhancing its system-level solution capabilities.
Currently, global panel-level packaging is overall in the ramp-up stage of pilot production and small-batch trial production, with obvious shortcomings still existing in yield, capacity, and the industrial ecosystem. Liao Yujun believes that the core tasks for the industry at this stage are very clear: simultaneously advancing yield improvement, capacity expansion, and cost reduction. The three are closely linked; only when a substantive breakthrough in yield is achieved can the capacity dividends brought by large substrates be truly transformed into cost advantages.
Considering the R&D and production line layout pace of global enterprises, Liao Yujun believes that the next 3 to 5 years will be a critical breakthrough cycle for panel-level packaging. As materials, equipment, and inspection processes are continuously refined, coupled with the acceleration of collaborative innovation across the industry chain, the industry is expected to usher in a dual turning point in yield and cost, gradually moving towards scaled commercial shipments.
Author: Gu Yue
Editor: Qiu Jiangyong, Art Editor: Maria, Supervisor: Lian Xiaodong