On August 13, 2026, the 5th Dishui Lake China RISC-V Industry Forum was successfully held at the InterContinental Shanghai Dishui.
Qiu Jianle, Vice President of R&D at Timesintelli, was invited to attend and introduced the company's purely domestic, high-performance, and robust NIC chip—the PT153S.
Figure | Qiu Jianle, Vice President of R&D at Timesintelli
Founded in Zhangjiang, Shanghai in 2018, Timesintelli focuses on three business areas: RISC-V processors, edge AI accelerators, and ASIC custom chips. All its product lines are equipped with self-developed RISC-V processors.
When it comes to the PT153S, Qiu Jianle described the chip as "a single chip that handles USB Gigabit networking."
Specifically, the PT153S is a USB-to-Gigabit Ethernet NIC chip. Launched in December last year, its shipments exceeded one million units by March and April this year.
From a technical perspective, the PT153S is an interface chip with straightforward functions: one end features USB 3.2 Gen1 to connect to a PC or host at a speed of 5Gbps, compatible with SS/HS/FS full-speed modes; the other end is a Gigabit Ethernet port for connecting network cables, supporting 10/100/1000M auto-detection and auto-negotiation. The core control section in the middle utilizes Timesintelli's self-developed RISC-V processor core.
Using RISC-V for a NIC is not exactly revolutionary, but Timesintelli made some specific trade-offs with this chip. Conventional USB NIC chips are often built using a hardware state machine plus a small MCU (Microcontroller Unit), or by directly purchasing an ARM core license.Timesintelli chose to integrate its most familiar RISC-V core, delegating tasks such as USB protocol and enumeration, Ethernet link management, power and low-power control, and continuous firmware evolution to it.
Qiu Jianle believes that the advantages of RISC-V lie in its open and royalty-free nature, which saves IP licensing fees; its instruction set can be extended for specific applications; its ecosystem is steadily maturing, with GCC, LLVM toolchains, and RTOS under active development; and its architecture is independently controllable, providing greater assurance for supply chain security.
For network packet processing, Timesintelli has implemented several dedicated instruction extensions. Operations such as checksum calculation, wake-up packet matching, and byte order conversion do not rely on the CPU for brute-force computation, saving both time and power compared to general-purpose instructions.
Figure | Actual performance testing, comparable to international mainstream solutions; Source: Timesintelli
Actual test results show that the PT153S achieves an iperf throughput of around 950Mbps, approaching the theoretical Gigabit limit. Its power consumption and temperature rise are comparable to mainstream competitors on the market. It supports three power modes: Normal, Powersaving, and Sleep, with power consumption dropping to as low as 10mW in Sleep mode. It also supports Wake-on-LAN, including three wake-up methods: Magic Packet, Wake-up Frame, and Link Change, allowing the network to seamlessly recover after the host is woken up.
Qiu Jianle pointed out that the biggest barrier for NIC chips is not actually performance, but compatibility. Protocol handshakes between different operating systems, motherboards, and switches involve a massive number of edge cases to handle. International leading brands have been working on this for over a decade, refining their solutions across various scenarios.
TimesIntelli has currently completed compatibility with Windows, Linux, macOS, Android, and HarmonyOS, enabling driver-free direct connection. It supports hardware offloading of TCP/UDP checksums for IPv4 and IPv6, 802.1Q VLAN, and 802.3az Energy-Efficient Ethernet, as well as IEEE 1588v1/v2 Precision Time Synchronization. The company's next step is to tackle gaming console platforms, with support expected in 3 to 6 months.
In addition, Qiu Jianle introduced some engineering details of the chip itself. The PT153S integrates an LDO and DC-DC, featuring a highly simplified peripheral circuit. It comes in a QFN40 package measuring 5mm x 5mm, taking up minimal board space. The SiP integrates 1Mb of Flash for firmware storage, supporting online upgrades and mass production calibration, and can also accommodate customized differentiation for customers. In terms of ESD, the HBM reaches 4kV, and the network port cable reaches 10kV. It has passed traffic testing under high and low-temperature environments of -40°C/+85°C without failing.
Notably, the chip features a pin-to-pin compatible design in its hardware pins, allowing customers to directly replace it without modifying the board. Meanwhile, the supply chain for this chip is entirely domestic, which is a hard requirement for customers in the information technology application innovation (Xinchuang) sector.
Figure | Timesintelli provides a complete hardware and software solution related to the PT153S; Source: Timesintelli
The motivation behind Timesintelli developing this chip is quite straightforward: AI chips are tough to develop and struggle to achieve high volumes, so the company sought a category that could scale up quickly. Although the unit price of NIC chips is not high, the market is stable with substantial replacement demand. As long as the pins and drivers are compatible, customers are willing to try them. The practical application scenarios are also very clear. The simplest is the USB external NIC—laptops are becoming increasingly thin, and wired Ethernet ports have been largely eliminated. It can also be used in docking stations, desktop PC motherboards, or embedded industrial motherboards.
The PT153S is not a chip that pursues the ultimate limits of performance; it focuses more on stability, compatibility, and low replacement costs. By applying RISC-V in a mature and established market and relying on precise control over cost and compatibility, it achieved a volume of one million units in three months. Timesintelli provides complete hardware and software solutions, offering chips, development boards, and product reference designs directly, so customers basically do not need to start from scratch. This approach currently proves to be viable.