Author: ICVIEWS Editorial Department
In recent years, the global semiconductor industry has accelerated its shift towards more advanced process nodes and higher integration levels. Applications such as AI (Artificial Intelligence), high-performance computing, and advanced storage continue to drive chip performance upgrades. As one of the most core and complex processes in IC (Integrated Circuit) manufacturing, lithography technology directly affects the process node, performance, power consumption, and yield of chips, becoming a key force driving the continuous evolution of the semiconductor industry.
From September 10 to 11, the 10th International Workshop on Advanced Photolithography and Patterning (IWAPS) was held at the Shenzhen World Exhibition & Convention Center. Experts, scholars, corporate representatives, and industry technicians in the field of lithography from home and abroad gathered in Shenzhen to conduct in-depth exchanges on the latest progress, industrial applications, and future trends of advanced lithography technology.
This year's IWAPS was hosted by the Chinese Optical Society (COS), co-organized by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS), China International Optoelectronic Exposition (CIOE), Lithography Equipment Manufacturing Technology Innovation Center, and Nanjing Chengxin IC Technology Research Institute Co., Ltd., co-organized by the School of Integrated Circuits, University of Chinese Academy of Sciences (UCAS) and the Lithography Technology Professional Committee of the Chinese Optical Society, with ICVIEWS as the cooperative media.
Over ten editions of cultivation, relying on China's fertile ground for innovation, IWAPS has continuously built a global exchange platform for advanced lithography technology. From the first conference to the present, IWAPS has witnessed the continuous evolution of global lithography technology and has become an important link connecting cutting-edge research, industrial demands, and technical practices.
Liu Xu, Secretary-General of the Chinese Optical Society, Fellow of COS, OPTICA, and SPIE, Professor at Zhejiang University, and Director of the State Key Laboratory of Modern Optical Instrumentation; Cao Jianlin, Chairman and Director of Jihua Laboratory and IWAPS Co-Chair; Ye Tianchun, Researcher at the Institute of Microelectronics of the Chinese Academy of Sciences, IEEE Fellow, and IWAPS Co-Chair; Li Ling, Deputy Director of the Institute of Microelectronics of the Chinese Academy of Sciences and Deputy Dean of the School of Integrated Circuits at UCAS, and other distinguished guests attended the opening ceremony and delivered speeches. Tan Jiubin, Academician of the Chinese Academy of Engineering and Professor at Harbin Institute of Technology, delivered a speech via video. The opening ceremony was hosted by Wei Yayi, Professor at UCAS, Researcher at IMECAS, Fellow of SPIE and COS, and Secretary-General of the IWAPS Conference.
Liu Xu, Secretary-General of the Chinese Optical Society, Fellow of COS, OPTICA, and SPIE, Professor at Zhejiang University, and Director of the State Key Laboratory of Modern Optical Instrumentation, stated that the 10th IWAPS is an important milestone in the development of the conference. Held in Shenzhen and concurrently with the China International Optoelectronic Exposition (CIOE), this edition will further promote exchanges and interactions between lithography technology and the optoelectronic industry, building an open window for cooperation for the global optical, academic, and industrial communities. Given the rapid evolution of AI technology, the IC industry is ushering in new development opportunities, and the importance of advanced lithography and patterning technologies is further highlighted. Against the backdrop of a continuously evolving global landscape, deepening international academic exchanges and industrial cooperation is more critical than ever. He expressed his expectation that expert representatives from universities, research institutes, and enterprises will fully exchange ideas, build consensus, and jointly promote the development of related technologies and industries.
Cao Jianlin, Researcher, Chairman and Director of Jihua Laboratory, and IWAPS Co-Chair, expressed that as IWAPS reaches its 10th edition, looking back at the history of the conference from a new development node brings many emotions. Combining his decades of experience in scientific research in short-wave optics, optoelectronics, and related equipment industries, he reviewed how his mentor, Mr. Wang Daheng, promoted the development of China's optical industry. From going overseas to study soft X-ray optics in the 1980s to witnessing the accelerated development of China's optical, semiconductor, and IC industries today, he deeply feels that China's relevant scientific research capabilities, industrial foundation, and innovation system have made significant progress. He pointed out that lithography is a crucial process in chip manufacturing, integrating the most cutting-edge science and technology in advanced equipment, materials, and processes. Its development level is directly related to the innovation capacity of the entire IC industry. Facing changes in the global industrial landscape and future challenges, segments of the industry chain such as processes, equipment, materials, packaging and testing, and downstream applications need to further strengthen collaboration to promote the deep integration of technology and industrial resources. He stated that after ten editions, the scale and industry influence of IWAPS have continued to increase. In the future, it will continue to gather strength from all parties, promote exchanges and cooperation, and strive to make each conference better than the last.
Ye Tianchun, Researcher at the Institute of Microelectronics of the Chinese Academy of Sciences, IEEE Fellow, and IWAPS Co-Chair, stated that as the complexity of advanced process nodes and R&D costs continue to rise, competition in the IC industry has shifted from merely pursuing device dimension scaling to collaborative innovation in design, process, equipment, materials, software, and system architecture. Competition in lithography technology has also extended from exposure resolution and overlay accuracy to the entire chain, including light sources, optical systems, masks, photoresists, computational lithography, inspection and metrology, and process integration. The development path is shifting from single technology breakthroughs to comprehensive competition in system capabilities. Lithography is a highly complex systems engineering project. Equipment capabilities determine the physical boundaries, materials and processes determine manufacturability, EDA and computational lithography determine whether design intent can be accurately translated onto the wafer, and inspection and metrology determine whether the manufacturing closed-loop can continuously converge. Looking to the future, it is necessary to further unblock all segments of the industry chain, leverage systematic approaches such as computational lithography, process modeling, DTCO (Design-Technology Co-Optimization), and STCO (System-Technology Co-Optimization), and form continuous innovation capabilities targeting advanced nodes, specialty processes, and advanced packaging. IWAPS will also continue to gather global wisdom, promote the deep integration of industry, academia, and research, and contribute to the technological progress of the semiconductor industry.
Li Ling, Deputy Director of the Institute of Microelectronics of the Chinese Academy of Sciences and Deputy Dean of the School of Integrated Circuits at UCAS, stated that lithography technology has always played an irreplaceable role in the development of the IC industry. Lithography precision not only defines the minimum feature size of chips but also marks every technological node in the evolution of Moore's Law. Currently, the classic scaling path faces physical limit challenges, while the industry's demand for low-power, high-performance chips is becoming increasingly urgent, posing higher requirements for lithography technology. Against this backdrop, it is necessary to further deepen international cooperation, strengthen interdisciplinary integration, and jointly promote new breakthroughs in lithography technology.
Tan Jiubin, Academician of the Chinese Academy of Engineering and Professor at Harbin Institute of Technology, delivered a speech via video. He stated that lithography technology sits at the top of the precision chain in the modern scientific and technological industrial system. It is an important commanding height of human manufacturing capability before entering atomic-level manufacturing, continuously leading the chip and semiconductor industries towards the extremely microscopic scale. Lithography is not only an extremely precise manufacturing process but also a complex technical system integrating precision optics, advanced materials, high-end equipment, ultra-precision measurement, computational methods, intelligent control, and semiconductor manufacturing processes. IWAPS has developed into an important international exchange platform connecting academic research and industrial practice, playing a crucial role in assessing technology trends, identifying key bottlenecks, promoting interdisciplinary cooperation, and driving the engineering and industrialization of scientific research achievements. The Division of Information and Electronic Engineering of the Chinese Academy of Engineering will support the continuous development of IWAPS and, together with relevant academic organizations and industry alliances, enhance the strategic leading role and industry influence of the conference, providing strategic, intellectual, and technical support for the long-term development of the global chip and semiconductor industries.
Wei Yayi, Professor at UCAS, Researcher at IMECAS, Fellow of SPIE and COS, and Secretary-General of the IWAPS Conference, reviewed the development history of the first nine editions of IWAPS. He stated that since the first conference, the scale of participation, number of presentation applications, and paper submissions for IWAPS have continued to grow, attracting numerous experts, scholars, and industry professionals from around the world. This year, IWAPS will continue to deepen cooperation with the International Society for Optics and Photonics (SPIE), jointly promote the development of advanced lithography and patterning technologies, and further build a global network for technical exchange and cooperation.
01 Exploring Future Lithography Directions
Currently, the global lithography industry is entering a new stage of collaborative innovation in equipment, materials, processes, software, and metrology. EUV (Extreme Ultraviolet) Lithography and High-NA EUV technologies continue to advance process verification, immersion DUV lithography continuously expands its application potential, and advanced packaging and heterogeneous integration bring more high-precision patterning demands. Meanwhile, AI and machine learning are accelerating their integration into computational lithography, process modeling, and metrology analysis, driving lithography technology from single-capability breakthroughs to whole-industry-chain collaborative optimization. At the symposium, experts and scholars in the field of lithography technology from home and abroad will take the stage one by one to share new breakthroughs achieved in various frontier topics, showcase academic achievements, and announce technology development results and products.
Dr. Wang Han, Professor and Deputy Head of the Department of Electrical and Electronic Engineering, The University of Hong Kong: Novel Nanomaterial Composite Masks for Advanced EUV Lithography
The pellicle used for advanced lithography is a key component in semiconductor manufacturing for protecting masks. Its optical transmittance, thermal stability, and long-term reliability directly affect chip manufacturing yield and lithography equipment production efficiency. Traditional pellicles face increasingly severe challenges under high-power exposure conditions.
This presentation will introduce a thin-film technology based on a novel nanomaterial composite system. This technology simultaneously features high optical transparency and enhanced durability. This novel film structure exhibits excellent particle protection capabilities, heat resistance, and operational reliability, providing a promising material platform for advanced lithography.
The EUV mask pellicle originated from an IBM patent in 1978. Its core principle is to use a separation distance to keep particles falling on the pellicle out of focus, avoiding imaging defects on the wafer. EUV lithography uses a 13.5 nm reflective optical system, and the EUV beam passes through the pellicle twice, imposing four hard requirements on the pellicle: high EUV transmittance, high thermal stability, hydrogen plasma resistance, and good particle blocking capability; under exposure conditions, the pellicle temperature can reach 500-800 °C.
EUV pellicles have undergone multiple generations of technological evolution. The first generation (2006-2015) featured grid-supported silicon-based thin films, where the support grid caused light blocking and uneven illumination, resulting in significant optical loss. The second generation (2013-2016) introduced grid-free self-supporting thin films, eliminating the support grid and relying on the film's own tension to maintain the structure, with radiative heat dissipation of ultra-thin films becoming the main technical challenge. The third generation (2016-2021) utilized polysilicon stacked films, which is also ASML's existing product. Different layers respectively undertake mechanical support, hydrogen plasma protection, and radiative heat dissipation functions, with a single-pass transmittance of about 85%, compatible with 250 W light sources. The fourth generation (2018-present) is based on MoSi composite thin films, belonging to the industrial silicide technology route, integrating multiple functions within a single composite film layer: MoSi is responsible for radiative heat dissipation, relying on emissive silicide grains to enhance cooling capacity under a given thermal load; the silicon matrix provides mechanical support, carrying grains in the tensioned film, with grain size determining device reliability; this solution has a single-pass transmittance of about 87%-90%, compatible with 400-450 W light sources. The fifth generation (since 2021) features carbon nanotube (CNT) thin films. The porous CNT network has thermal stability greater than 2000 °C. imec has completed scanner full-field exposure tests, with bare CNT single-pass transmittance reaching up to 97%; however, bare carbon nanotubes are etched by hydrogen plasma, limiting practical use.
Addressing the shortcoming of bare CNTs in hydrogen plasma tolerance, The University of Hong Kong proposed a CNT-BNNT core-shell composite scheme (BNNT refers to boron nitride nanotubes), adopting a one-dimensional core-shell structure where boron nitride nanotubes coaxially wrap carbon nanotubes. This structure maintains over 95% EUV single-pass transmittance, achieves excellent hydrogen plasma resistance, and extends the lifespan by about 10 times compared to pure CNTs. The team has obtained multiple authorized US patents and has several patents pending, completing the intellectual property layout for this structure and preparation process.
Looking to the future, the industry is developing kilowatt-level EUV light sources and High-NA EUV systems. The thermal load is further increasing, and the importance of mask protection is growing. CNT composite films coated with BNNT are candidate solutions for next-generation high-power EUV pellicles. Subsequent efforts need to advance the engineering development of CNT-BNNT composite films for kilowatt-level EUV light sources.
Professor Lu Ye, Fudan University: How is AI Disrupting Fundamental Chip Design and DTCO?
As Moore's Law approaches physical limits, the semiconductor industry is undergoing a paradigm shift from solely relying on process scaling to Design-Technology Co-Optimization (DTCO). Against the backdrop of increasingly complex transistor structures and high R&D costs for advanced process nodes, traditional design methods relying on manual experience can no longer cope with the challenges of multiple physical effects. By breaking down data barriers between design and manufacturing to achieve early feedback and global optimization, DTCO has become a critical path for improving chip Performance, Power, Area, and yield (PPA).
Traditional BSIM models (such as BSIM-SOI and BSIM-CMG) contain hundreds or even thousands of physical parameters, making their parameter extraction process extremely complex. Engineers need to follow a strict hierarchical process to sequentially fit key indicators such as mobility, series resistance, threshold voltage roll-off, velocity saturation, DIBL, self-heating effects, and noise. Since this process highly relies on manual experience and has a low error tolerance, deviations in any link can trigger cascading rework, causing the entire modeling cycle to often last for weeks or even months, severely constraining R&D efficiency.
To solve this pain point, Professor Lu Ye's team proposed the CDRPE (Automated Parameter Extraction combining Deep Learning and Reinforcement Learning) scheme. Its core logic is "DNN pre-training + RL fine-tuning": first, using Latin Hypercube Sampling (LHS) and SPICE simulations to generate 50,000 data points, pre-training through a Multi-Layer Perceptron (MLP), and then introducing reinforcement learning, using the simulator as the environment, and utilizing a multi-branch self-attention mechanism to allow the Agent to continuously fine-tune parameters under the guidance of physical knowledge.
Actual measurement results show that compared with traditional optimization methods (such as GA, DE, BO) and pure AI algorithms like PPO and DDPG, this CDRPE scheme has an extremely fast convergence speed, with a speed improvement of up to 8 times, and an RMSE (Root Mean Square Error) of less than 2%. More astonishingly, when facing different threshold voltages (LTV/HVT) and process corners (FF/SS), the tool can complete all extraction and verification within 1 hour, improving efficiency by 100 times compared to manual work. In addition, the team also developed a Multi-Gradient Neural Network (MNN) model, solving the problem of discontinuous high-order derivatives in traditional models, enabling it to perfectly fit TCAD data.
If DCM automation is laying the foundation, then AI generative analog circuit design is the superstructure. Unlike structured and highly automated digital ICs, analog/RF design is fragmented and tedious, highly relying on expert experience. The RFIC-GPT tool developed by Professor Lu Ye's team has completely changed this situation. This tool can generate high-frequency analog devices, circuit schematics, and even GDSII layouts that meet specifications within seconds, with an accuracy of over 95% and without the need for repeated iterations; it also supports core modules such as inductors, transformers, matching circuits, and amplifiers, covering CMOS processes from 130 nm all the way to the most advanced 6 nm.
Looking to the future, Professor Lu Ye proposed the frontier concept of the "Large DTCO Model". He stated that AI is reshaping the DTCO process, opening a brand-new feedback loop for fast DTCO and AI-EDA. From device modeling to circuit generation, and from parameter extraction to layout output, AI is no longer just an auxiliary tool in the chip design process, but is becoming a new engine running through the collaborative optimization of the entire industry chain.
Professor Lin Nan, Beihang University: Solid-State Laser-Driven LPP-EUV, Exploring New Routes for EUV Light Sources
The Laser-Produced Plasma Extreme Ultraviolet (LPP-EUV) light source is the core of EUV lithography equipment, and its Wall-Plug Efficiency (WPE) is directly related to the operating cost and power scaling capability of the light source. For a long time, commercial LPP-EUV light sources have mainly used CO₂ lasers (10.6 μm) to drive tin droplets to generate 13.5 nm EUV radiation. However, limited by the wall-plug efficiency of the CO₂ laser itself and the laser-plasma interaction mechanism, the system WPE of the first mass-produced EUV equipment (NXE:3400) is only about 0.13%. High energy consumption and operating costs have become important bottlenecks restricting further power improvement and large-scale application of EUV light sources.
Professor Lin Nan's team has conducted research on 1 μm and 2 μm solid-state laser-driven LPP-EUV light sources to further improve the system wall-plug efficiency. Solid-state lasers have high wall-plug efficiency (about 10%-20%), and shorter laser wavelengths will bring different laser-plasma interaction mechanisms, which are expected to simultaneously improve laser wall-plug efficiency (L-WPE) and conversion efficiency (CE). To support this research, the team built a multi-diagnostic EUV light source research platform, integrating various diagnostic methods such as electron density diagnostics, plasma imaging, EUV emission spectroscopy, ion energy spectroscopy, and laser Thomson scattering. They also independently developed a 13.5 nm in-band radiation power meter and an EUV flat-field grating spectrometer, providing an experimental foundation for light source optimization.
Experimental results show that in single-pulse mode, the 2 μm solid-state laser-driven scheme achieved an L-WPE of about 10% and a CE of 4.3%, with a total WPE reaching 0.43%. The WPE of the 1 μm scheme reached 0.44%. Both are more than 3 times that of the traditional CO₂ laser double-pulse scheme (0.13%), reaching a domestically leading and internationally advanced level. Through an emission-absorption double-layer radiation model, the team deeply studied the variation law of the optical thickness of the inner and outer layers of the plasma with laser intensity, finding that EUV re-absorption is an important factor limiting further improvement of CE, providing direction for subsequent optimization. In addition, in the optimization of broadband EUV radiation for metrology applications, the team adopted a 1 μm spatial confinement scheme to achieve a broadband conversion efficiency of 52.5%, exceeding the previous similar results of about 45%, reaching a relatively high level reported in this band.
Solid-state laser-driven LPP-EUV is moving from laboratory research to more in-depth performance verification. It is expected to reduce the operating costs and energy consumption of EUV light sources through higher wall-plug efficiency without changing the EUV exposure optical architecture, while providing a new technical path for the development of higher-power EUV light sources. In the future, as the solid-state laser architecture is further upgraded, plasma physics is continuously optimized, and systems engineering is continuously improved, solid-state laser-driven LPP-EUV is expected to further advance towards industrial applications.
Kris Leask, R&D Engineer at Mycronic: Cost-Effective Overlay Metrology Solution for Binary and Phase-Shift Masks
Driven by server and storage applications, the semiconductor market is expected to maintain a compound annual growth rate of 8% over the next five years. Meanwhile, the shipment volume of I-line and KrF lithography equipment continues to grow, providing strong support for the photomask market at mature technology nodes. However, in the traditional node field with 90 to 250 nm design rules, photomask metrology has long faced the problems of traditional equipment approaching end-of-life, overcapacity and excessively high costs of high-end metrology tools. The market urgently needs a modern metrology system that matches the needs of mature nodes.
MMX is a new generation of pattern position measurement system developed by Mycronic based on the SLX laser mask writer platform. It was officially launched and the first unit was delivered in 2024. The system adopts a custom optical measurement module (405 nm laser illumination), an improved interferometer positioning system, and a new edge detection algorithm. Through the user-friendly workflow of MyMAX script editing, MMX measurement, and Myra data analysis, it balances measurement speed and operating costs, supporting 5 to 9-inch masks and processing up to 24 masks per batch.
In binary mask evaluation, targeting CoG, KrF-HT, and ArF-HT three substrates, MMX showed highly consistent repeatability across all evaluated pattern types, always below 3.5 nm, pattern-induced shift controlled within ±2 nm, and measurement grid accuracy reaching ±4 nm. Under a 40 nm position tolerance, the Gage R&R is 9.3% to 9.9%, indicating that it can meet the metrology needs of photomasks at mature nodes.
In phase-shift mask (PSM) metrology, although the multi-layer structure brings additional challenges such as reduced image contrast and phase modulation, MMX maintains position repeatability below 3 nm on both MoSi and quartz layers, and the %GRR for three-tone layer shift measurement is only 0.60% to 0.96% under an 80 nm tolerance. In rigorous testing of asymmetric three-tone structures, MMX detected small and stable direction-dependent deviations, consistent with the trend of shorter-wavelength high-end reference systems, demonstrating robust measurement fidelity.
In the above research, Measurement System Analysis (MSA) was used for repeatability and reproducibility analysis. The results confirm that MMX can meet the metrology needs in photomask production at mature technology nodes while balancing measurement capability and operating costs. Combined with the MYIntelligence intelligent digital solution, MMX can also realize data interconnection in writing, measurement, inspection, and correction links, further expanding its application value in the photomask production process.