GD32F103XX 108M时钟配置【转】

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GD32F103XX 108M时钟配置【转】

通过HSE(8MHz)得到108MHz SysClk的配置过程：

1. static void SetSysClockTo108(void)
   
2. {
   
3.   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
   
4.   
   
5.   /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/   
   
6.   /* Enable HSE */   
   
7.   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
   
8. 
   
9.   /* Wait till HSE is ready and if Time out is reached exit */
   
10.   do
    
11.   {
    
12.     HSEStatus = RCC->CR & RCC_CR_HSERDY;
    
13.     StartUpCounter++;  
    
14.   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
    
15. 
    
16.   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
    
17.   {
    
18.     HSEStatus = (uint32_t)0x01;
    
19.   }
    
20.   else
    
21.   {
    
22.     HSEStatus = (uint32_t)0x00;
    
23.   }  
    
24. 
    
25.   if (HSEStatus == (uint32_t)0x01)
    
26.   {
    
27. 
    
28.     /* HCLK = SYSCLK */
    
29.     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
    
30.       
    
31.     /* PCLK2 = HCLK */
    
32.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
    
33.    
    
34.     /* PCLK1 = HCLK */
    
35.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
    
36.    
    
37.     /*  PLL configuration: PLLCLK = HSE/2* (15+12) = 108 MHz */
    
38.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
    
39.                                         RCC_CFGR_PLLMULL));
    
40.     RCC->CFGR |= (uint32_t)(0x08000000 | RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL12);
    
41. 
    
42.     /* Enable PLL */
    
43.     RCC->CR |= RCC_CR_PLLON;
    
44. 
    
45.     /* Wait till PLL is ready */
    
46.     while((RCC->CR & RCC_CR_PLLRDY) == 0)
    
47.     {
    
48.     }
    
49.    
    
50.     /* Select PLL as system clock source */
    
51.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
    
52.     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   
    
53. 
    
54.     /* Wait till PLL is used as system clock source */
    
55.     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
    
56.     {
    
57.     }
    
58.   }
    
59.   else
    
60.   { /* If HSE fails to start-up, the application will have wrong clock
    
61.          configuration. User can add here some code to deal with this error */
    
62.   }
    
63. }
    
64. 
    
65. 通过HSI(8MHz)得到108MHzSysClk的配置过程
    
66. 
    
67. static void SetSysClockTo108(void)
    
68. {
    
69.    /* HCLK = SYSCLK */
    
70.     RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
    
71. 
    
72.     /* PCLK2 = HCLK */
    
73.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
    
74.    
    
75.     /* PCLK1 = HCLK */
    
76.     RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
    
77.    
    
78.     /*  PLL configuration: PLLCLK = HSI/2* (15+12) = 108 MHz */
    
79.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL));
    
80.     RCC->CFGR |= (uint32_t)(0x08000000 | RCC_CFGR_PLLSRC_HSI_Div2  | RCC_CFGR_PLLMULL12);
    
81. 
    
82.     /* Enable PLL */
    
83.     RCC->CR |= RCC_CR_PLLON;
    
84. 
    
85.     /* Wait till PLL is ready */
    
86.     while((RCC->CR & RCC_CR_PLLRDY) == 0)
    
87.     {
    
88.     }
    
89.    
    
90.     /* Select PLL as system clock source */
    
91.     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
    
92.     RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;   
    
93. 
    
94.     /* Wait till PLL is used as system clock source */
    
95.     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
    
96.     {
    
97.     }
    
98. }
    
99. 
    
100. 
     
101. 
     
102. 如果使用串口
     
103. 还应该修改 RCC_GetClocksFreq 函数，以获得正确的系统时钟，具体修改方法
     
104. 
     
105. 
     
106. RCC_GetClocksFreq的修改：
     
107. 先修改以下几个值：
     
108. #define CFGR_PLL_Mask             ((uint32_t)0xF7C0FFFF)
     
109. #define CFGR_PLLMull_Mask         ((uint32_t)0x083C0000)
     
110. #define CFGR_ADCPRE_Reset_Mask    ((uint32_t)0xEFFF3FFF)
     
111. #define CFGR_ADCPRE_Set_Mask      ((uint32_t)0x1000C000)
     
112. 
     
113. static __I uint8_t ADCPrescTable[8] = {2, 4, 6, 8, 2, 12, 6, 16};
     
114. 
     
115. 修改函数：
     
116. void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
     
117. {
     
118.   uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
     
119. 
     
120.   /* Get SYSCLK source -------------------------------------------------------*/
     
121.   tmp = RCC->CFGR & CFGR_SWS_Mask;
     
122. 
     
123.   switch (tmp)
     
124.   {
     
125.     case 0x00:  /* HSI used as system clock */
     
126.       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
     
127.       break;
     
128.     case 0x04:  /* HSE used as system clock */
     
129.       RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
     
130.       break;
     
131.     case 0x08:  /* PLL used as system clock */
     
132. 
     
133.       /* Get PLL clock source and multiplication factor ----------------------*/
     
134.       pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
     
135.       pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
     
136. 
     
137.       if(((pllmull)&(0x08000000)) != 0)
     
138.           pllmull = (((pllmull)&(0xF7FFFFFF)) >> 18) + 17;
     
139.       else
     
140.           pllmull = ( pllmull >> 18) +2;
     
141. 
     
142.       if (pllsource == 0x00)
     
143.       {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
     
144.         RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
     
145.       }
     
146.       else
     
147.       {
     
148.         /* HSE selected as PLL clock entry */
     
149.         if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
     
150.         {/* HSE oscillator clock divided by 2 */
     
151.           RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
     
152.         }
     
153.         else
     
154.         {
     
155.           RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
     
156.         }
     
157.       }
     
158.       break;
     
159.     default:
     
160.       RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
     
161.       break;
     
162.   }
     
163. 
     
164.   /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
     
165.   /* Get HCLK prescaler */
     
166.   tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
     
167.   tmp = tmp >> 4;
     
168.   presc = APBAHBPrescTable[tmp];
     
169.   /* HCLK clock frequency */
     
170.   RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
     
171.   /* Get PCLK1 prescaler */
     
172.   tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
     
173.   tmp = tmp >> 8;
     
174.   presc = APBAHBPrescTable[tmp];
     
175.   /* PCLK1 clock frequency */
     
176.   RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
     
177.   /* Get PCLK2 prescaler */
     
178.   tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
     
179.   tmp = tmp >> 11;
     
180.   presc = APBAHBPrescTable[tmp];
     
181.   /* PCLK2 clock frequency */
     
182.   RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
     
183.   /* Get ADCCLK prescaler */
     
184.   tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
     
185. tmp = ((tmp >> 14)&(0xF))+(tmp >> 26);
     
186.   presc = ADCPrescTable[tmp];
     
187.   /* ADCCLK clock frequency */
     
188.   RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
     
189. }

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