On the Eve of Industrial Transformation: System Applications Driving the Reconstruction of EDA
Over the past year, the most profound change in the global technology industry has occurred at the intersection of the physical world and digital intelligence. From the rapid iteration of embodied intelligence and the city-level deployment of autonomous driving, to various robots beginning to enter industrial and household scenarios, AI (Artificial Intelligence) is extending from virtual space to the physical world at an unprecedented pace.
This transformation is not a single-point breakthrough, but a bottom-up, multi-layered technology chain. System applications at the very forefront—whether autonomous vehicles requiring real-time perception and decision-making, or industrial robots demanding high autonomous execution capabilities—are imposing fundamental new requirements on underlying chips: higher energy efficiency, stronger heterogeneous computing capabilities, and more complex multi-chip collaborative architectures. Chips are no longer just "computing components," but the neural center of the entire intelligent system.
This demand pressure is directly transmitted to the chip design level. Traditional planar, single-chip design methodologies are being replaced by system-level architectures such as 3D-IC and Chiplet, with design scales leaping from hundreds of millions of transistors to tens of billions or even hundreds of billions. Issues such as power consumption, heat dissipation, signal integrity, and multi-physics field coupling are intertwined, causing the design space to expand exponentially. Meanwhile, dynamic adjustments in the global supply chain, fluctuations in memory and computing power costs, and customers' continuous exploration of ultimate design spaces all present R&D teams with unprecedented comprehensive challenges.
As chip complexity approaches the limit of manual optimization by human engineers, the EDA industry finds itself at a crossroads of transformation. Traditional design tool flows can no longer match the pace of chip architecture innovation—a single advanced process node chip often requires 40 to 60 backend engineers, verification takes up more than half of the entire development cycle, and the sign-off convergence stage is filled with a massive amount of repetitive and tedious engineering labor. Relying solely on increasing the number of engineering personnel to cope with growing complexity has proven to be an unsustainable development approach.
It is precisely against the backdrop of this drastic industrial change that the CadenceLIVE China User Conference was recently held in Shanghai. As one of the top three global EDA giants, Cadence sent a clear strategic signal at this conference: AI agents are evolving from auxiliary tools into core productivity engines for chip and system design, and the mission of the EDA industry is shifting from "providing tools" to "building intelligent system design platforms."
Dr. Jin-Qing Teng, Senior Vice President and General Manager of the Digital & Signoff Group at Cadence, frankly stated, "Relying solely on increasing the number of engineering personnel is not a sustainable development approach. The industry is also actively seeking a new direction of development, hoping to integrate AI into the design process to improve productivity. In fact, this is precisely the opportunity to truly create value for everyone."
Dr. Jin-Qing Teng, Senior Vice President and General Manager of the Digital & Signoff Group at Cadence
From the demand pressure of system applications, to the complex evolution of chip architectures, and then to the intelligent reconstruction of EDA tools, a clear chain of transformation has taken shape. What Cadence showcased at this user conference is precisely the very end of this chain—and also the most leveraged link—how to redefine the methodology of chip and system design through AI.
Paradigm Shift from "Optimization AI" to "Agentic AI"
In Dr. Teng's view, the development of AI in the EDA field has undergone a clear evolutionary path: from the early "Optimization AI" (capable only of rule optimization), to "Conversational LLMs" (capable of simple interaction and reasoning), and now truly entering the era of "AI Agents."
"AI agents can not only answer questions but also proactively complete a large number of complex engineering tasks, truly beginning to change the way engineers work," Dr. Teng stated.
Behind this transformation is the "three-layer cake" concept proposed by Cadence. Dr. Teng elaborated on this architecture in his speech: the top layer consists of AI agents, responsible for intelligent decision-making and task orchestration; the middle layer comprises core algorithms based on physics, mathematics, and computer science, covering all simulation and optimization engines; and the bottom layer is the accelerated computing platform, including CPUs, GPUs, and various dedicated accelerators.
Dr. Teng used a vivid metaphor, "You cannot achieve excellent autonomous driving on a car with ordinary performance. Similarly, if you want AI to truly deliver value in the design flow, you must first have world-class design tools, and then add AI."
This concept profoundly reveals the essence of AI adoption in the EDA industry—AI is not a replacement for tools, but a multiplier that amplifies tool capabilities. Every bit of capability improvement in the middle layer will be amplified by AI, but if there are inherent problems in the middle layer itself, even the strongest AI cannot yield results.
Full-Stack AI Agents: Complete Coverage from Chip to System
In April this year, Cadence officially released the complete AgentStack architecture at the CadenceLIVE Silicon Valley 2026 conference. This is a unified Super Agent capable of coordinating all specialized agents, and it can scale from chip design to 3D-IC design, and further to system design and analysis.
Under this architecture, Cadence has developed multiple specialized AI super agents for different design segments:
ChipStack is targeted at digital front-end design and verification, covering RTL generation, testbench creation, regression test orchestration, and debugging. Dr. Teng pointed out that RTL is essentially a programming language describing chip functions, and AI can help engineers write code more efficiently. However, insufficient training data is the biggest challenge—the scale of RTL data is much smaller than that of general-purpose programming languages, and most IPs are core assets of various companies and are not publicly available.
To address this, Cadence proposed the RL² (Reinforcement Learning Squared) architecture: the first reinforcement learning loop is responsible for determining the design architecture and ensuring logical functional correctness, while the second loop meticulously refines the architecture to achieve optimal PPA (Performance, Power, and Area).
ViraStack is targeted at analog and custom design, a field where the degree of automation has been limited over the past few decades because analog design involves a large number of non-linear and multi-physics challenges, with extensive design experience held by senior engineers. ViraStack can automatically retrieve internal design projects and IP libraries, and automatically invoke tools to complete parameter tuning and optimization. According to Dr. Teng, after a key customer adopted ViraStack, within just one month, the number of their internal engineers using ViraStack expanded from 10 to 100, and then grew to a scale of 500.
InnoStack is targeted at digital back-end implementation and signoff, ranging from synthesis, place and route, to signoff analysis and ECO execution. The biggest challenge faced by large chip companies is a severe shortage of back-end engineers—a 1-million-gate chip requires at least 40 to 60 back-end engineers. The goal of InnoStack is to enable a single AI agent to handle 3, 4, or even more modules simultaneously.
AuraStack is the world's first AI agent for advanced PCB (Printed Circuit Board) and advanced packaging design, covering key stages from system planning and design implementation to signoff quality review.
Dr. Teng specifically emphasized, "Our goal is not just to embed AI into tools, but we also hope that new agents can collaborate to help customers achieve a truly meaningful fully intelligent design platform."
AI Does Not Replace Engineers, But Amplifies Them
In the opening remarks by Xiaoyu Wang, Vice President and General Manager of China and Southeast Asia at Cadence, there is a passage worth savoring repeatedly, "Our original intention is very pure, just like when EDA first emerged. The AI agents doing so much today are not meant to replace human engineers. Instead, we hope to help technical personnel hand over extremely tedious engineering problems to AI for intelligent processing, allowing our technical experts and personnel to focus their intelligence and energy on the most core and challenging R&D work."
Xiaoyu Wang, Vice President and General Manager of China and Southeast Asia at Cadence
This concept was supported by specific data in Dr. Teng's speech. In the signoff convergence stage, for a 28nm high-efficiency core, human engineers spent about 20 hours to achieve convergence, while the AI agent reduced violations by 58% on the first run for the same design. In the field of simulation verification, violations were reduced by 79% within a month. For a total of 40 hours of work, the AI completed it in 8 hours, saving 28 hours of senior engineers' time.
NVIDIA CEO Jensen Huang expressed a similar view when he shared the stage with Cadence CEO Anirudh Devgan at the CadenceLIVE Silicon Valley conference in April this year. Jensen Huang pointed out, "We have now reached a node where agents can anticipate, reason, and execute plans. AI has gone from knowing everything and being able to spit out various knowledge and information, to now being able to use tools." He further stated that agentic systems can scale engineering capabilities by allowing engineers to coordinate multiple specialized agents simultaneously.
Hardware Acceleration and 3D-IC: Dual Engines for Next-Generation Design
In addition to AI agents, Cadence is also continuously focusing on two directions: hardware acceleration and 3D-IC.
In terms of hardware acceleration, Cadence's Palladium Z3 and Protium X3 platforms have experienced rapid business growth over the past six years. Each cabinet contains over 100 chips, all tightly connected with fiber optics, representing a complete system engineering achievement. More importantly, Cadence is actively promoting GPU acceleration—starting this year, many core algorithms have supported GPUs, providing customers with a 5x to 10x performance improvement.
In the field of 3D-IC, Dr. Teng pointed out, "3D-IC is not a new concept; it has been around for about 20 years, but its era has just begun." Cadence launched the Integrity 3D-IC platform, integrating chip design tools, packaging design platforms, and electrical, thermal, and mechanical analysis tools. The most critical breakthrough is that Cadence has significantly upgraded the underlying architecture, integrating the Z-axis dimension into the core algorithms—traditional planar placement algorithms mainly consider the X and Y dimensions, whereas 3D-IC requires considering the physical constraints of the Z-axis from the very beginning.
Physical AI: The Next Trillion-Dollar Track
Looking at a longer time dimension, Dr. Teng depicted a more imaginative picture—Physical AI.
"In the next 2 to 7 years, we will usher in the next important stage of development, including Physical AI—various types of robots, drones, and autonomous driving will be widely used in our lives and production processes," Dr. Teng stated.
Physical AI requires AI models to not only understand human language and data but also comprehend the physical laws of the real world. This will impose entirely new requirements on next-generation chips, giving birth to more innovative chip architectures.
Jensen Huang's speech at CadenceLIVE echoed this, "Just as we once had the ChatGPT moment—the generative AI moment for language—we have now reached the generative AI moment for robotics. It is called VLA: Vision-Language-Action model, which is basically perception input and action output."
Dr. Teng provided a more macroscopic industry judgment, "Many industry leaders believe that future humanoid robots could become one of the largest product categories in human history, with the potential to reach a scale of $25 trillion annually. For reference, the current global GDP is only $110 trillion."
In the field of Physical AI, Cadence possesses the world's most advanced physical simulation technologies such as Clarity and Celsius. High-fidelity physical simulation combined with accelerated computing enables users to achieve a 10x to 500x performance improvement while maintaining physical accuracy standards. This means customers can not only rapidly generate a massive amount of high-quality training data but also more effectively validate model performance in the real world.
Deepening Roots in China: From EDA Tools to System Innovation
Xiaoyu Wang specifically emphasized the strategic significance of the Chinese market, "For Cadence, we will stick to our original intention, continue to expand and increase our investment in China, and deepen our roots in the Chinese market. We will use our product strength, especially our most grounded services, to walk side by side with you and contribute to your success."
He observed that profound changes are taking place among Chinese customers, "The chip and system design industry is undergoing a massive and rapid shift. It is not just about pursuing the scaling down of physical process nodes; at the same time, we are seeing more and more customers, especially Chinese customers, fully entering the era of system innovation, architectural innovation, and ecosystem building, and now fully embracing the era of AI agents."
This observation echoes Cadence's own strategic transformation. Cadence invests 35% to 40% of its annual revenue in R&D. The company has approximately 15,000 employees, of which 14,000 are engineers—a 10,000-strong R&D team and a 4,000-strong application engineering team, fighting side by side with customers every day. Over half of the employees hold master's degrees or above, including more than 1,000 Ph.D.s from top global universities.
Dr. Teng stated, "All the best innovations are absolutely not made in isolation; good enterprises and good products are usually the result of successful collaboration. We hope to continue cooperating with our customers in the future to jointly define next-generation chips and systems, and jointly create the future."
Conclusion
From market expectations of $1.3 trillion to $2 trillion, from the paradigm shift from Optimization AI to AI agents, to the industrial extension from chip design to Physical AI—the signals released by the CadenceLIVE China User Conference 2026 are clear and strong: the semiconductor industry is standing at the starting point of a profound transformation, and AI-driven intelligent system design is the core engine of this transformation.
For China's chip design industry, this is both a challenge and, more importantly, an opportunity. As Xiaoyu Wang said, "Facing infinite challenges in the future, there are also infinite possibilities." In the new era of deep integration between AI and chip design, enterprises that can take the lead in transforming AI agents into productivity will seize the initiative in the next round of industrial competition.