"In the future, the overall AI will see significant improvements driven by the synergy between algorithms and hardware-software co-optimization. Hardware might push the overall AI performance up by 30% to 40% at most, but the synergy between algorithms and hardware-software co-optimization will absolutely leave room for a 10x or even 100x improvement in the future," said Guo Weijun, Vice President of Marketing at MoXin AI Technology (Shenzhen) Co., Ltd., at the recently held ICDIA.
Founded in 2018, this AI chip company is attempting to carve out a differentiated path in the fierce competition of domestic AI chips by adopting the technical route of "sparse computing".
Guo Weijun, Vice President of Marketing at MoXin AI Technology (Shenzhen) Co., Ltd.
Over the past two years, the domestic AI chip industry has undergone a critical transition from "availability" to "superiority". Companies such as Moore Threads, Muxi, and Biren have successively completed large-scale deployments, bringing domestic AI chips into the deep waters of commercialization. However, in Guo Weijun's view, a fundamental issue remains unresolved—computing power cost.
"Currently, the vast majority of edge deployments are quite difficult," Guo Weijun stated frankly in his speech. "In the future, the biggest challenge for every GPU company will be how to apply their various architectures, heterogeneous designs, and near-memory computing into production tools."
The persistently high cost of Tokens is becoming a bottleneck restricting the scaled development of the AI industry. From cloud providers to individual developers, the pressure of inference costs is increasing day by day. MoXin's chosen approach to solving this problem is to delve deep into a technical direction that was once relatively niche but has now become crucial for breaking the AI computing cost bottleneck—sparse computing, a field they have been deeply engaged in for seven years.
Sparse Computing: Not an Algorithm, but a "Production Tool"
Sparse computing is not a new concept. NVIDIA introduced 2:4 structured sparsity technology as early as the Ampere architecture era, which retains 2 non-zero elements out of every 4 consecutive weights, achieving a 50% sparsity rate and theoretically doubling the matrix multiplication throughput. However, Guo Weijun pointed out that MoXin's understanding of sparsity goes far beyond this.
"Sparsity itself is a set of production tools," Guo Weijun repeatedly emphasized this point in the interview. "It is not just a mathematical term; it is a complete suite of production tools. At the design level of the entire chip, have you developed sparse operators for the chip? Have you made adjustments at the scheduling layer? And have you independently developed sparse computing units similar to MPUs or SPUs?" This is a systematic engineering effort.
There is a dedicated chip area in MoXin's chips called the SPU (Sparse Processing Unit). "This is unique in the domestic chip architecture field; it is a dedicated area specifically designed to accelerate the sparsity of the entire operator."
Guo Weijun further explained the essential logic of sparse computing: "In the future, you cannot search for something in a large model, such as 'what to do for a toothache?', and still invoke tens of billions of parameters for calculation; there is absolutely no need for that. In future functions, when a user mentions a toothache, this sparse function might quickly schedule to the operator layer, invoking only parameters in the medical field, and might only need 70B compute to solve the problem."
In his view, the core value of sparse computing lies in shifting AI inference from "brute-force computing" to "precise computing"—"In the future, a major issue that most cloud providers, including Token factories, will have to consider is whether to reduce our model accuracy or if it is just OK to meet the production cost."
Differentiated Path: From SPU to SP200
In the domestic AI chip sector, MoXin's technical route appears quite unique.
"We are the only company in China betting on the sparse computing track," Guo Weijun admitted frankly. "Therefore, our target positioning is relatively clear."
This uniqueness is reflected in the underlying design of the hardware architecture. Unlike the industry's common practice of "performing compression and pruning at the model layer," MoXin's sparsification is "embedded" during the chip design phase. "Our algorithm turns most of the redundant parts in current models that can be converted into hardware-efficient, regularized sparse elements into functions, and then possibly embeds them at the SPU stage."
From the perspective of the product line, MoXin's first-generation products—the S40 card and S10 card—are mainly targeted at small-parameter models and industry vertical models. Guo Weijun revealed that the company already has commercial deployments in vertical fields such as security and life sciences: "For example, in domestic protein base detection, which is a highly vertical field, you will find that sparsity has extremely unique advantages in the computing field of small models. Because it absolutely does not require such high energy consumption or such a large parameter scale."
The upcoming second-generation product, SP200 (SparsePrime), is a flagship product aimed at large-scale inference scenarios. According to Guo Weijun, this chip "focuses on the exclusive track for future inference and delivers outstanding performance in terms of Prefill and decode."
In terms of performance metrics, MoXin's S30 computing card has topped the MLPerf Inference leaderboard for three consecutive times, demonstrating leading energy efficiency and inference throughput per unit of compute in mainstream tasks such as vision, natural language processing, and large models. Regarding this, Guo Weijun stated, "We are confident that after this card is launched in the future, it will be able to break into the top 5 among existing domestic inference cards."
Realistic Challenges: Process Node, Memory, and Trade-offs
Beyond the technical vision, Guo Weijun has a clear understanding of the realistic dilemmas faced by domestic AI chips.
"Currently, manufacturing capacity and process nodes are very critical factors for the entire industry," he stated frankly. "The industry is undergoing drastic changes; the entire AI industry has experienced earth-shattering changes in the past half year. How exactly do we adapt to these industrial changes?"
Faced with these constraints, the underlying chip architecture for sparse computing is still in the exploratory stage, and it is essentially a matter of "trade-offs". "What kind of dynamic balance is appropriate? How much space should be left for general-purpose chips to perform computational inference, how much for dynamic scheduling, how much for computing units, and how much area should be allocated?" Guo Weijun revealed that MoXin spent a considerable amount of time evaluating the architecture verification of the SP200, "which is all about calculating and balancing these issues."
He cited specific performance metrics: "We have conducted a large number of tests for first-token latency P99, and also made substantial compromises and compatibilities regarding the timeliness of throughput."
At the software level, the challenges are equally significant. "Current software tools are also continuously iterating and updating to provide better adaptability for large models. That is why I say sparse computing is a systematic engineering project; it is not just about developing an algorithm. No, the challenges are immense."
Industry-University-Research Layout: Targeting the Frontier of "Sparse Training"
Beyond technological breakthroughs, MoXin has also made systematic arrangements at the industry-university-research level.
In August 2026, the "MoXin Sparse Computing Industry-University-Research Alliance," initiated by MoXin AI, was officially established, gathering renowned universities such as Tsinghua University, Fudan University, Xi'an Jiaotong University, and Nankai University, as well as leading industry partners including BGI Group, China Mobile, INESA, VeriSilicon, and ASR Microelectronics.
Guo Weijun specifically emphasized the collaboration with the mathematics department: "This year, we have engaged in significant collaboration with the entire Department of Applied Mathematics at Xi'an Jiaotong University at the sparse matrix level. We predict that a key direction for the country's subsequent AI development will revolve around the field of mathematics."
He explained the reason for choosing the mathematics department over the microelectronics department: "Most models are still at the matrix layer, and sparsity at the matrix layer should still be a mathematical issue—not basic mathematics, but applied mathematics."
A more long-term goal is "sparse training". "In the future, we hope to reach the training layer at the sparse training layer during the chip design phase, rather than doing calculations at the KD, CoT, FFN, and N-call stages," Guo Weijun mentioned. "In the future, all foundation model companies, when doing early foundation model training, will integrate sparse training functions into the construction of the foundation models."
He revealed, "In the future, after our cards are back, we will focus on the frontier fields of sparse training in industry-university-research and conduct in-depth cooperation with the vast majority of domestic large model companies. This is a very important direction to further elevate our domestic model capabilities in the future."
Conclusion
From its establishment in 2018 to the present, MoXin has been on the path of sparse computing for seven years. At the industrial turning point where domestic AI chips are moving from "brute-force computing" to "precise computing," the company is attempting to answer a core question with a full-stack sparse solution ranging from chip architecture to software stack: how to make AI inference cheaper and more efficient.
"Sparse computing is not an optional choice in future technical routes," Guo Weijun mentioned. "AI inference will shift from complete brute-force computing to a precise computing path in the future." The realization of this judgment in the market, and the market performance of the SP200 upon its launch, will be the key validation. Under the realistic constraints of limited process nodes and limited memory, the "trade-off" path chosen by MoXin may well be a microcosm of domestic AI chips seeking differentiated breakthroughs.