The National Center for Technological Innovation in Integrated Circuit Design Automation (referred to as the "National Center for Technological Innovation in EDA" or "EDA National Innovation Center") was approved by the Ministry of Science and Technology on December 30, 2022. It is led by Southeast University and co-built with the Jiangbei New Area of Nanjing, leading domestic EDA enterprises, and research institutes. As the first and only national-level technological innovation center in the field of IC (Integrated Circuit) design in China, over the nearly four years since its establishment, it has been exploring a different path from the more than 70 domestic EDA companies—rather than developing traditional EDA tools, it is using AI to reconstruct the entire chip design process.
"If AI can design chips, how should we coexist with machines." At the recently held ICDIA, Yang Jun, Executive Director of the EDA National Innovation Center and Chief Professor at Southeast University, posed this proposition. By "AI designing chips," he does not mean AI-assisted design, but rather points to a more radical vision—"Intelligent EDA, computing all circuits."
Yang Jun, Executive Director of the EDA National Innovation Center and Chief Professor at Southeast University
"If it is AI + EDA tools, it can design a series of chips simultaneously," Yang Jun pointed out. In his view, traditional chip design requires a research and development cycle of half a year to two years, involving dozens to hundreds of people, with labor costs accounting for 60% to 70%. He proposed a bold vision for industrial transformation: the emergence of the Fabless model in the 1980s shared manufacturing costs among multiple design companies; in the future, a new business model of "Designless" may emerge—"System companies can also design chips, and design companies might only need 1/10 of their original scale to achieve the original product portfolio."
Agentic AI in the Verification Stage: Replacing Junior Engineers, but the "Last Mile" Remains a Challenge
Chip verification is one of the most time-consuming stages in the design process. The normal ratio of design engineers to verification engineers is about 1:2 to 1:3. What can and cannot Agentic AI do in this stage? Jiang Zhe, PI of the iDebug project team at the EDA National Innovation Center and faculty member at Southeast University, provided an answer based on practice.
Jiang Zhe, PI of the iDebug Project Team at the EDA National Innovation Center and Faculty Member at Southeast University
"In terms of writing code, or translating verification cases into specific test code, large models or Agentic systems are already doing a very good job," Jiang stated. What does this represent? Previously in the verification pipeline, a large amount of this work was done by junior engineers—fresh graduates who, after experienced engineers made the plans, "just needed to write the code."
Current problems and challenges lie in two areas. The first is early-stage chip verification planning: "After a chip is developed, where exactly should I verify it? Large models do not perform particularly well here, because they always generate something, but is it actually good? It still requires manual review." The second is the complex scenarios of the "last mile": "A chip needs to be tested in various scenarios, and there are always a few scenarios at the end. In this 'last mile' stage, Agentic systems do not perform well."
"Fortunately, the work of making plans actually does not require many people. Generally, one or two very senior engineers are enough for a project, while the vast majority of engineers are very junior," Jiang summarized. "Agentic systems can replace many junior engineers."
At the deployment level, Agentic EDA tools face equally realistic challenges. "Chip companies strongly dislike uploading their data to the internet or sharing their data with others," Jiang admitted. "In addition, the chip design industry is a relatively closed one, where different companies have their own specifications or processes. The specifications written by Company A and Company B are different; adjustments made for Company A's specifications might not work well for Company B."
From Research to Commercialization: The Birth of iDebug and Ultra-Low-Cost Physical Design
A unique feature of the EDA National Innovation Center is its "industry-university-research closed-loop" mechanism—forming a complete transformation path from scientific research to industrial incubation.
The iDebug project team is exactly a product of this mechanism. "We are doing incremental work, not replacing any domestic toolchains," Jiang emphasized. "We utilize their existing tools to achieve faster and more efficient usage on top of them." He cited the collaboration with Empyrean Technology as an example: "They develop simulators. We do not build the simulators ourselves; instead, we use our technology to accelerate their simulation, or use our Agentic systems to operate their simulators."
In 2025, the EDA National Innovation Center and X-EPIC jointly released ChatDV, a large model for digital chip verification based on LLMs (Large Language Models). ChatDV pioneered the iModel, iSVA, iTest, and iDebug large models, building an intelligent verification framework. In June 2026, the first incubated enterprise of the EDA National Innovation Center, Zhiwei Chuangxin (Nanjing) Technology Co., Ltd., completed an angel round financing of tens of millions of RMB, focusing on chip verification large models and one-click generation of chip IP.
In the field of automated physical design, the National Innovation Center has launched a Multi-Agent system. Yang Jun introduced that its core lies in three points: breaking down all place and route tools into many micro-tools; conducting massive attribution analysis; and performing batch processing and parallelization.
Market Opportunities for Domestic EDA: Customized Scenarios and AI-Native Processes
When asked about the market opportunities for domestic EDA, Jiang Zhe proposed two directions.
The first is customized scenarios. "Products made by leading enterprises might be more general; they will not optimize or customize for a single scenario. But if my EDA tool only needs to perform CPU simulation or synthesis, it can actually be done very quickly."
He believes the emergence of large models makes this opportunity more realistic: "Writing code has become incredibly cheap. What does this represent? This is a good thing; we indeed have the opportunity to do some customized work."
The second is the reconstruction of AI-native processes. "A true point for overtaking on a curve is whether we can use large language models to rewrite this process? We can replace many manual tasks with AI to shorten the entire tape-out cycle," Jiang proposed. "Large language models are something newly emerged. Compared to the 70 to 80-year history of EDA, it is actually a very, very new thing, and everyone is starting from the same new starting line."
Conclusion
From its approval in 2022 to the present, the EDA National Innovation Center has walked a nearly four-year path of exploration. In Yang Jun's view, the slogan "Intelligent EDA, computing all circuits" proposed by the National Innovation Center is a "beautiful vision," but "we are moving forward slowly, step by step."
From the incubation of iDebug to the "ultra-low-cost" promotion of automated physical design, from cooperation with domestic EDA manufacturers to the service implementation with enterprises such as Xiaomi and CETC, the National Innovation Center is exploring a new path from "choke points" technological research to industrial application.