On September 10, the Ministry of Industry and Information Technology (MIIT) and the National Development and Reform Commission (NDRC) jointly issued the "15th Five-Year Plan for the Development of the Electronic Information Manufacturing Industry" (MIIT Joint Regulation [2026] No. 216), which was released in a centralized manner from September 15 to 16. In this top-level document, which targets a revenue of over CNY 30 trillion for enterprises above designated size and an R&D intensity of 3.5% by 2030, RISC-V is explicitly mentioned as a five-year plan task for the first time.
I. Policy Review
The expressions regarding RISC-V in the original text of the plan focus on two main threads:
First, R&D and industrialization. The document explicitly states "promote the R&D and industrialization of the fifth-generation reduced instruction set computer (RISC-V), and support the application of RISC-V chips in fields such as AI (Artificial Intelligence) and embedded systems." This marks the first time RISC-V has been explicitly mentioned in the form of a national five-year plan task, elevating the policy level from past "spontaneous enterprise exploration" to a "national strategy."
Second, systematic planning of computing power infrastructure. The plan lists new computing paradigms such as HBM/HBF new memory, computing-storage integration, optical computing, and neuromorphic computing as key tasks, and supports "hundreds of thousands of cards" AI (Artificial Intelligence) clusters; at the same time, it incorporates photonics, Advanced Packaging, and EDA/IP cores into the "foundation building" main line. RISC-V, new memory, Advanced Packaging, and domestic EDA are linked into the same logical chain of the "independent computing power root technology stack."
The overall approach is "building the foundation, improving quality, fostering innovation, and governance," with the plan deploying 17 key tasks and supporting multiple special columns.
II. Industrial Impact
First, let us look at the strategic logic. The approach of the plan is very clear: use open-source instruction sets + domestic EDA to bypass the authorization walls of ARM/x86, and then use new memory, computing-storage integration, and photonic interconnects to make up for the shortcomings in computing power and bandwidth. It is not about competing head-on with x86/ARM on the old track, but changing the root technology stack to start a new game. The judgment of Cang Wei, Vice President of Xpeedic, hits the nail on the head—the more advanced computing advances, the more it relies on system capabilities. "Supporting roles" such as HBM, Chiplet, Advanced Packaging, high-speed interconnects, and liquid cooling will become the "leading roles." The next stage task of domestic EDA is not just to fill the gap in tools, but also to support advanced chips and packaging in entering complex engineering R&D.
Industry two-way impact. The benefit chain is direct and clear: RISC-V chip companies, advanced manufacturing processes, new memory (HBM/HBF), and Advanced Packaging—related enterprises will be the first to reap the policy dividends; local supporting policies and industry-finance integration will be implemented around the 17 tasks and multiple special columns, accelerating demonstration projects, standard projects, and subsidies. In contrast, the long-term ARM and x86 ecosystems may be substituted, putting pressure on the relevant industrial chains.
Key enterprises are already in place. According to the first-half review by China Electronics News, multiple manufacturers such as ESWIN Computing, Lingrui Zhixin Computing Technology, Nuclei System Technology, and Lanxin Computing are accelerating the promotion of projects compliant with the RVA23 specification; Alibaba DAMO Academy's Xuantie C950 (SPECint2006 exceeding 70 points), CAS's "Xiangshan-Kunming Lake" (16.5 points/GHz + open-source interconnect "Wenyu River"), and SpacemiT K3 (the world's first mass-produced RVA23 chip) have formed an echelon in the high-performance segment. Among them, ESWIN Computing, as a chip product provider based on the RISC-V architecture, follows the RISC-V+AI route: the automotive CMS master control EAI8800 is built-in with three self-developed RISC-V cores and has obtained dual certifications of ASIL-B and AEC-Q100; the multi-purpose intelligent computing SoC (System on Chip) EIC7702 is equipped with a 64-bit RISC-V processor, targeting machine vision and commercial robots; the RISAA ecosystem technology platform covers the device-edge-cloud continuum. This combination of "mass-produced products + specification tracking + ecosystem platform" is exactly the industrialization form that the policy wants to see.
The industrialization path of RISC-V: a long way to go! Writing the "industrialization" of RISC-V into the national strategic plan does not mean that high-end data center CPUs can compete head-on with x86 and Arm tomorrow. The improvement and maturation of the software ecosystem, including OS, compilers, and basic software libraries, still require the joint efforts of the entire industrial chain. After all, "Rome was not built in a day."
III. Market Assessment
SHD Group predicts that global RISC-V SoC (System on Chip) shipments reached approximately 6.9 billion units in 2025, and are expected to exceed 36 billion units by 2031, with the market size surpassing USD 300 billion, at a compound annual growth rate of 31.7%.
Ni Guangnan, an academician of the Chinese Academy of Engineering, gave a more intuitive scale at the 2026 Xuantie RISC-V Ecosystem Conference: the global share of RISC-V has exceeded 25%, meaning one out of every four processors shipped globally is RISC-V; China's RISC-V chip shipments exceed 3 billion units, accounting for more than half of the global total.
The high-value battlefield of servers is also accelerating—data from industry research institution IIM shows that global RISC-V server chip shipments reached approximately 4.2 million units in 2025, a year-on-year increase of 133%, and are expected to rise to 9.5 million units by the end of 2026. The market size was USD 420 million in 2025 and is expected to exceed USD 8.7 billion by 2030.
These figures, combined with the intensive industrialization actions this year—the mass production and delivery of the RVA23 specification, the approval of the RISC-V Server Platform Specification 1.0, the rollout of the Lanxin LX500 mass-produced server, and Ubuntu 26.04 LTS using RVA23 as the baseline—all point to a judgment: RISC-V has passed the technology validation period and entered the explosive stage of large-scale commercialization. The "tripartite landscape" is no longer just a vision, but an industrial reality that is happening.
The leading domestic enterprises at the table are worth tracking: ESWIN Computing (RISC-V+AI, full-stack automotive/interconnect/computing), Alibaba DAMO Academy (Xuantie high-performance CPU), CAS (Xiangshan open-source root technology), SpacemiT (RVA23 AI (Artificial Intelligence) CPU), Lingwise, and Lanxin Computing (server-level cores and mass production platforms). They represent several paths, respectively, including vertical scenarios and mass production implementation, as well as high performance and open-source foundations. For manufacturers like ESWIN Computing that focus on RISC-V+AI, the plan has written the direction into national documents, but the real test lies outside the documents—whoever can run through the ecosystem first and turn products into solutions that customers are willing to pay for will be able to capture this round of policy dividends.
The plan has pointed its pen to RISC-V, but whether RISC-V can truly take a seat at the table depends on who can run through commercialization first in the next three years.