As Moore's Law approaches its physical limits, advanced packaging and 3D stacking are becoming critical paths for sustaining chip performance improvements. According to market research firms, the global 2.5D and 3D IC packaging market is expected to reach $12.4 billion by 2026 and is projected to grow to $33 billion by 2034. The Chiplet market is also experiencing rapid growth, with its scale expected to reach $65.3 billion by 2026.
However, the flip side of market enthusiasm is a sharp increase in technical difficulty. The EDA tools and methodologies accumulated during the 2D chip design era are facing the pressure of reconstruction in 3D stacking scenarios. It is against this backdrop that Silicon Core Technology, founded in December 2022, is attempting to forge a differentiated path in the "uncharted territory" of 3D IC EDA.
At the recently held ICDIA Exhibition, Zhao Yi, Founder and General Manager of Zhuhai Silicon Core Technology Co., Ltd., explicitly pointed out, "Adding a vertical dimension directly leads to an explosive growth in the solution space, which is exactly a quantitative change producing a qualitative leap."
This judgment points to the fundamental challenges that 3D IC poses to EDA tools.
3D Placement and Routing: From "Quantitative Change" to "Qualitative Leap"
"The release of Tao's Law perfectly reflects what the actual differences are between 3D and 2D placement and routing," Zhao Yi stated while answering questions from eefocus journalists, first distinguishing between two levels: "quantitative change leading to qualitative leap" and "essential qualitative leap."
The quantitative change leading to a qualitative leap is reflected in the explosive growth of the solution space. Zhao Yi gave an example, "When doing 2D placement and routing for 10,000 modules, the permutations and combinations to find the optimal positional solution are already numerous. But with 3D vertical stacking, there can be over 10,000 TSVs between two layers. Just adding these TSVs to permute and combine for the optimal positional solution results in an astronomical number."
Even more complex is "logic folding"—splitting the same circuit module across different chip layers. "First, it's splitting one into two; why not split one into four? This is like origami, essentially partitioning the granularity. When the overall design has three layers, combination issues also arise—how many parts to divide into? Which layer should Part 1 and Part 2 be placed on?"
"When you have 10,000 modules that can all be partitioned this way, the solution space increases by several orders of magnitude. It looks like a quantitative change; previously there might have been 100 million solutions, now there could be 10 quadrillion solutions. This means the underlying algorithms must undergo a thorough and complete transformation."
The essential qualitative leap is even more disruptive. Zhao Yi pointed out that when modules are split across different layers, "different dies will most likely not use the same process node"—the compute module might adopt 7nm, and the I/O module might adopt 10nm. After implementation in different process nodes and then connected, "placement and routing are no longer suitable for seeking purely logical solutions; it introduces physical attributes into the equation."
"In the past, within a single SoC (System on Chip), it was unheard of for one SoC to have different process nodes. But in 3D stacking, this has completely changed."
The second qualitative leap lies in the definition of the "optimal path." "Generally speaking, the optimal path is finding the shortest interconnect path. However, during 3D stacking, devices between layers will affect each other, and interconnects will affect adjacent transistors. We can no longer just look at the shortest distance—if this path is the shortest but affects the performance of adjacent power lines, how do we weigh the trade-offs? If this path requires TSVs, and the TSVs will impact adjacent transistors, how do we make the choice?"
"The optimal path mentioned in Tao's Law must be a multi-objective collaborative optimal path. This sounds simple, but for the essence of the entire algorithm, the essence of the methodology, including the placement and routing solver, it is a concept on an entirely different level."
From DTCO to STCO: Simulation Shift-Left and Cross-Scale Challenges
The transformation in design methodology is equally profound. Zhao Yi pointed out that traditional single-chip design follows the DTCO (Design-Technology Co-Optimization) methodology, whereas 3D stacking requires a shift towards STCO (System-Design-Technology Co-Optimization).
"Simulation tools can no longer be used as before, where various simulations—signal, power, and thermal—are run only after completing the design and drawing the layout. This approach is no longer viable because it will face an overwhelming number of iterations and callbacks. Simulation needs to be shifted left as early as possible."
However, shifting simulation left brings new problems. Zhao Yi stated, "The earlier you go, the less information you have. During architectural planning, the placement doesn't even exist yet, so how can you know the actual future routing? Even if you find an estimation method, can you use a high-precision simulation engine to do it? Wouldn't that be a waste of time? Shifting left means doing fast simulation, and fast simulation means modifying the simulation engine."
The challenges of multi-physics simulation are even more prominent. "At the solver level, Maxwell's equations are for electromagnetics, and partial differential equations are for heat conduction—the underlying mathematical algorithms are completely different. Previously, simulation engines had their respective suitable scenarios; now, handling them in a unified manner poses a tremendous difficulty."
Cross-scale issues are an even "bigger challenge" in 3D stacking. "Simulations are required inside the chip, and after stacking, it must interconnect with the substrate, package substrate, and PCB (Printed Circuit Board). The accuracy requirements inside the chip are much higher, and it is very difficult to simulate the interconnects of multi-layer stacking and the VR of hybrid bonding. Not to mention from inside the die to outside the die, or from die to die."
Zhao Yi pointed out the solution approach: "First, mixed-scale simulation is definitely required; second, AI (Artificial Intelligence) methods will inevitably be introduced in the future."
Full-Flow Platform and AI Empowerment
The core product of Silicon Core Technology is the self-developed 3Sheng Integration Platform, which integrates five core centers: system-level architecture design, physical implementation, multi-die test and fault tolerance, analysis and simulation, and multi-Chiplet verification. According to the company, this platform is one of the few domestic EDA platforms that possess a full-flow stacked chip design toolchain.
"Our characteristic lies in the relatively broad coverage of the toolchain, from architecture to physical design, to simulation and verification, and even Design for Testability (DFT)," Zhao Yi stated. "The data at every stage can be interconnected within our own data foundation and our tool platform."
In terms of AI empowerment, Silicon Core Technology has launched Chips Z, a dedicated AI Agent platform for 2.5D/3D heterogeneous integration design. "Through the AI Agent approach, we automatically iterate and select design algorithms, and through continuous case learning, we enable the tools to achieve better engineering implementation."
Zhao Yi explained the necessity of AI in 3D IC EDA: "New design methods will encounter multi-generational iterative processes. When new tools are truly implemented in engineering, they lack engineering accumulation. Here, AI can help with automatic iteration and optimization."
Customer Ecosystem and Differentiated Advantages
Regarding product implementation, Zhao Yi listed multiple customer groups: "Many companies wanting to develop computing-in-memory chips will inevitably move towards 3D stacking—3D DRAM multi-layer stacking and computing-in-memory IC (Integrated Circuit) design companies urgently need a completely new toolchain."
"Edge computing chips have demands for computing power and space, forcing them to move towards 3D stacking. Some CPU makers are adding 3D DRAM on top of the CPU die; some dedicated edge image processing companies are combining NPU (Neural Processing Unit) with 3D DRAM. There is also the combination of DPU (Data Processing Unit) with 3D DRAM. For ultra-high bandwidth, when HBM (High Bandwidth Memory) cannot yet be stacked onto the logic die, they choose to place 3D DRAM on the DPU."
Regarding the company's differentiated advantages, Zhao Yi summarized them into three points: "First, our research started in 2008. We have accumulated a long history of know-how and technology transformation. The products themselves have barriers, and they cover quite a few sectors. Second, STCO requires end-to-end optimization. If the point tools for each stage are from different vendors—using Vendor A for architecture, Vendor B for placement and routing, and Vendor C for simulation—it is impossible to truly achieve closed-loop coupling. Merely connecting the process is far from enough; deep coupling at the code level is required for every stage. Third, while others have not yet assembled a complete toolchain, we have already started cooperating with many foundries and stacked chip design companies. This first-mover advantage is a threshold in another sense."
Conclusion
From starting research on stacked chip technology in 2008 to officially establishing the company in 2022, Silicon Core Technology has been deeply engaged in the 3D IC EDA track for over a decade. At the industrial turning point where 2.5D/3D advanced packaging shifts from an "optional choice" to a "mandatory choice," this startup is attempting to use a full-flow toolchain from architecture to verification to answer a core question: As chips move from 2D to 3D, how should EDA tools be reconstructed?
The explosive growth of the solution space from quantitative to qualitative change, the shift-left of multi-physics coupled simulation, and the cross-scale and cross-process collaborative optimization—the challenges brought by 3D stacking are far from being solved by simply "tweaking 2D tools." The path chosen by Silicon Core Technology is: starting from the reconstruction of underlying algorithms, building barriers through full-flow coverage and deep coupling between stages, and accelerating engineering implementation through the AI Agent platform.
"3D IC EDA is equivalent to a bridge," Zhao Yi defined it. Between advanced packaging processes and chip design, between system architecture and physical implementation, between simulation verification and design for testability—whether this bridge can truly connect all sectors of the industry determines the distance Silicon Core Technology can go from being a "first mover" to a "leader."