On September 4, He Tingbo, President of Huawei's Semiconductor Business Department, published the third academic paper on "Tao's Law" on ChinaXiv, the preprint platform of the Chinese Academy of Sciences, titled "Will Huawei's Tao Chip Melt?". This time, instead of just talking among themselves, Huawei put a mass-produced chip ready for shipment on the table, using actual test data to directly address the most pointed external doubts: Will 3D stacking overheat the chip?
01. From Planar Integration to 3D Integration
A hidden thread behind this paper is that it pushes the interconnect and Advanced Packaging processes, which have long been dependent on advanced process nodes, to the center of performance competition for the first time.
Guojin Securities pointed out in a review that Huawei's Tao's Law drives chips from planar integration to 3D integration, with process steps, interconnect counts, and manufacturing complexity rising simultaneously, which is a clear benefit for semiconductor equipment. Among them, "back-end testing" is a more direct incremental direction for Tao's Law—the increase in chip stacking layers and interconnect counts synchronously upgrades testing complexity, testing time, and yield management requirements, driving a multiplied growth in the demand for equipment such as test handlers, sorters, and probers.
Founder Securities, from the perspective of crowding, judges that the semiconductor industry is one of the few tracks that will maintain high prosperity in the coming years. Coupled with the incremental demand brought by domestic substitution and the expansion of advanced logic and storage capacity, the allocation value significantly increases after the crowding level falls back.
Behind this, there are also visible capacity expansion actions. OSAT leader JCET Group (600584) released a private placement plan of no more than CNY 6.5 billion on September 3, explicitly investing in the expansion of high-end Advanced Packaging platforms for high-performance computing, the upgrade of wafer-level packaging processes, and high-density memory packaging and testing projects. In the first half of the year, its revenue reached CNY 19.527 billion, and its net profit attributable to shareholders surged by 79.41% year-on-year. Leading enterprises are expanding capacity with real money, translating "3D chips are coming" from research report language into order language.
02. What Is Tao's Law?
What exactly do the three words "Tao's Law" mean?
For over half a century, the semiconductor industry has believed in Moore's Law—the number of transistors that can be accommodated on a chip of the same area doubles approximately every two years. The essence of this law is "spatial miniaturization": making transistors smaller and smaller, and placing them denser and denser. However, as process nodes advance to the few-nanometer level and approach physical limits, the path of continuing to rely on lithography machines to shrink transistors is becoming increasingly expensive and difficult.
Tao's Law, proposed by He Tingbo, provides another ruler—"temporal miniaturization". When a transistor is working, the real bulk of energy is not consumed in the logic operation of the transistor itself, but in the process of moving data from one place to another. The industry often says that over 80% of the energy in a chip module is spent on "commuting". Traditional 2D chips spread all circuits on a single plane. Signals have to run from one end of the chip to the other, traversing hundreds of micrometers or even longer wires. Every "long journey" burns electricity.
He Tingbo's idea is to fold the circuits like origami, replacing long horizontal routing with short vertical connections, allowing signals to "travel less". Since the passage of time is related to distance, shortening the distance of signal movement is equivalent to gaining precious time margin for the chip—this is exactly the connotation of "temporal scaling" in the word "Tao", and also the key difference from the spatial scaling of Moore's Law.
Here, a confusing concept needs to be clarified: Tao's Law does not mean that chips are naturally low-power and naturally cool because of this. He Tingbo repeatedly emphasized in the paper that Tao is a temporal scaling law, not an energy scaling law. For the time budget saved after folding, engineers can choose to operate at low voltage and low temperature, or choose to increase the frequency in exchange for stronger performance. Whether to save power or boost performance is essentially a trade-off in engineering. Precisely because of this, external intuitive doubts based on "the denser the stack, the hotter it must be" need to be re-examined in the face of Huawei's actual test data.
03. Actual Test Breakdown of Kirin 2026
The most naive concern from the outside world about 3D stacking is "the thicker the chip stack, the harder the heat dissipation"—with a significant increase in transistor density, power density should surge, and the chip should be hotter and more power-hungry. What Huawei presents this time is precisely the module-by-module actual test data for this mass-produced chip.
Combining He Tingbo's paper and previously disclosed data, the transistor density of Kirin 2026 has increased from about 155 million per square millimeter to 238 million, a leap of 55%. Under the test conditions of the same performance, compared with the previous generation of planar architecture chips, NPU power consumption decreased by 66%, GPU power consumption decreased by 58%, and CPU performance core power consumption decreased by 41%. The operating voltage dropped from 1.1V to 0.9V, the chip area shrank by 37.5%, and the clock frequency instead increased by 13%. The most typical example is the NPU module: under the premise of unchanged 29 TOPS computing power, the frequency decreased by 63%, the voltage dropped from 0.85V to 0.55V, and the power density decreased by 73%. The simultaneous improvement of density and power consumption in the same generation of products is contradictory under the logic of geometric scaling, but it is truly established in the actual test data.
Behind the anomaly is the reconstruction of principles. Logic folding significantly shortens the length of signal routing—the paper reveals that typical core routing can be shortened by about 20%, and some critical paths are shortened by up to 70%. Shorter routing directly reduces the interconnect capacitance overhead, which accounts for the bulk of power consumption. Since dynamic power consumption is proportional to the square of the voltage, the benefits are further amplified after the voltage is lowered. Huawei also listed a specific case: the clock routing of a certain processing module was shortened by 28%, and the number of clock buffers was directly reduced from 43,600 to 19,000, a cut of more than half. Tian Feng, Dean of the Fast and Slow Thinking Research Institute, pointed out the key to power saving when interpreting to Shanghai Securities News—the main cause of chip energy consumption is not "calculating a lot", but "moving signals far"; folding is equivalent to changing long routing on a plane into short 3D connections, allowing signals to travel less, and heat generation is naturally reduced from the source.
To address local high heat, Huawei provides two moves: first, reducing the power density at the source through folding to fundamentally prevent local high temperatures; second, proactively arranging heat dissipation during the design phase, placing the modules with the most severe heat generation in the positions with the most unobstructed heat dissipation paths. The paper even specifically lists a counterexample—although the power consumption of the first-generation stacking scheme for the DSP module decreased by 25%, due to a 40% shrinkage in area, the power density actually increased by 24%. It was not until the second-generation scheme that the density was truly brought down. This kind of proactive "self-exposure" honesty precisely shows that this is a systematic engineering project that requires repeated iterations, rather than a one-trick magic.
04. Interconnect Precision Takes Over from Lithography, Becoming the New Main Battlefield
The most far-reaching significance of Tau Scaling Law lies in changing the distribution of the industry value pool. In the past, chip performance improvement was almost equivalent to lithography process progress, and the imagination space of the industrial chain was firmly tied to the single question of "whether more advanced lithography machines can be bought". However, Huawei proved with Kirin 2026 that even without changing the lithography process, relying solely on architectural innovation can achieve dual improvements in performance and energy efficiency—this means that interconnects and Advanced Packaging will no longer just be "supporting roles" for advanced process nodes from now on.
The 3D interconnect pitch roadmap disclosed in the paper provides clear scales for this path: this generation of Kirin 2026 adopts a 1.5μm bonding pitch and about 50 million vertical interconnects per chip, all realized based on mature 40nm-class equipment, without the need for advanced EUV (Extreme Ultraviolet) Lithography machines throughout the process; the next-generation Kirin 2027 has reached the tape-out stage, and the bonding pitch of the actual tested silicon wafers has narrowed to 1μm, with over 100 million vertical interconnects; Huawei's more long-term goal is to advance to a 720nm pitch and over 200 million vertical interconnects within three years. The narrower the pitch, the more it means that the demand for hybrid bonding equipment, precision alignment, and high-purity bonding materials has become a certainty curve that is completely decoupled from the progress of lithography machines and can be continuously realized across multiple generations of products.
From the perspective of the industrial chain, the benefit logic unfolds sequentially along the upstream, midstream, and downstream.
The upstream provides materials and equipment for the interconnect foundation: hybrid bonding is considered the link with the highest certainty of domestic substitution in the entire chain. The wafer-to-wafer hybrid bonding equipment of Piotech (688072) has passed customer verification and received repeat orders. NAURA Technology (002371), HWATSING Technology (688120), Kingsemi (688037), and ACM Research (688082), among others, have formed synergy in supporting processes such as bonding, CMP, coating/developing, and cleaning.
The midstream is the Advanced Packaging and testing that truly "folds" the chips: the self-developed XDFOI multi-dimensional heterogeneous integration platform of JCET Group (600584) supports multi-layer active logic stacking and ultra-fine pitch hybrid bonding, and is regarded as one of the most mature platforms for the mass production support of logic folding. TFME (002156), Hua Tian Technology (002185), Yongsi Electronics (688362), and SJ Semiconductor (688820) are also in this track.
The downstream is design and verification tools. Empyrean Technology (301269) is one of the few domestic manufacturers that can provide full-process EDA for 3D heterogeneous integration design verification. Primarius Technologies (688206) and Semitronics (301095) form a supplement in device modeling and wafer yield testing. On the wafer manufacturing side, the mature process capacity of SMIC (Semiconductor Manufacturing International Corporation) (688981) and Hua Hong Semiconductor (688347) faces a revaluation of value due to this architectural path that does not rely on advanced lithography machines.
The Guojin Electronics team specifically named "back-end testing" as an easily overlooked but most direct increment: the increase in stacking layers and interconnect counts synchronously improves testing complexity, time, and yield management requirements, driving a multiplied growth in the demand for testing equipment. Jingzhida (688627) recently announced the signing of a CNY 1.576 billion procurement agreement for semiconductor testing equipment, which is being seen by the market as a signal that this link is entering large-scale volume production.
05. From Papers to Orders, Several Hurdles Remain to Be Cleared
No matter how attractive the technical route is, it ultimately comes down to whether it can be mass-produced and whether it can make money. The most solid part of this round of market trends is that Tau Scaling Law is no longer a theoretical deduction remaining on paper. Kirin 2026 has been taped out and is about to be shipped with the new autumn models, and Kirin 2027 has also completed tape-out. Huawei has proved with real mass-produced chips that 3D stacking is "feasible and cooler". He Tingbo even gave a long-term judgment in the paper: by 2031, the transistor density of high-end chips based on Tau Scaling Law is expected to reach the same level as advanced process nodes, without relying on corresponding advanced lithography equipment, and the evolution roadmaps for the next four generations of Kirin and Ascend are also laid out accordingly.
Capacity actions on the industrial side are in place simultaneously. JCET Group's CNY 6.5 billion private placement to increase investment in Advanced Packaging, and the prosperity of the domestic Advanced Packaging industrial chain being described by the industry as "booming", are all proofs that demand is landing. But what needs to be viewed calmly is that there are still several hurdles that must be crossed on this path. The paper currently only discloses performance and power consumption data, while yield and cost are not public—the yield of stacking two wafers is a multiplicative relationship, and the yield management pressure of multi-layer stacking cannot be underestimated. Whether mass production costs can be diluted with scale still awaits market testing after the real machines are launched in autumn. At the same time, Huawei frankly admits that single-threaded, non-parallelizable processor big cores are the link with the most limited benefits of this folding technology at present. To truly bring down the power consumption of big cores, it may require three to five years of high-intensity research. More importantly, 3D stacking and hybrid bonding are not Huawei's exclusive new inventions. Overseas foundry and IDM leaders have also been deeply involved in related fields for many years. Huawei's true moat lies more in the organizational integration capability of four-layer collaborative design of devices, circuits, chips, and systems, rather than a single isolated technical patent.
These reservations and honesty, on the contrary, make this narrative appear more credible—a company that dares to publicly release its technology roadmap and dares to admit that there are still unovercome shortcomings shows that it is not telling stories with PPTs, but is truly transforming physical laws step by step into reproducible engineering results.
06. Outlook: Another Possibility for Domestic Chips
Returning to the investment perspective, the most valuable thing brought by Tau Scaling Law is not necessarily a certain daily limit up, but a shift in thinking: when the physical limits of lithography machines seem impossible to cross by one's own efforts, can we bypass it and find another way through architectural and packaging innovation?
Huawei's answer is yes. It does not deny the value of advanced process nodes, but simply proves with Kirin 2026 that the path to semiconductor performance improvement is not just "shrinking transistors"—on mature process nodes, through 3D structuring and shortening signal paths, considerable density and energy efficiency dividends can also be exchanged. This route of "mature process + architectural innovation" complements the overseas path relying on extreme advanced process nodes, and also tears open an evolution window for domestic semiconductors that does not have to wait dead for EUV (Extreme Ultraviolet) Lithography. For the industrial chain, it elevates the interconnect, packaging, testing, and EDA links, which were previously dependent on the shadow of advanced process nodes, from "supporting" to the "main battlefield", allowing a group of domestic equipment, material, and tool manufacturers to get tickets for independent growth that can last for many years.
Of course, Rome was not built in a day. From the data in the paper to the orders expected by the market, there is a long process of yield ramp-up, cost dilution, and real machine verification in between, and emotional restlessness may also repeat before the data is realized. But looking at it from another angle, an industry being continuously driven by a clear and measurable technical direction is itself a rare certainty—it allows the market to no longer rely on guessing, but to verify step by step how far domestic semiconductors can go along the route of bonding pitch from 1.5μm to 1μm and 720nm. This road is destined to be bumpy, but at least, it puts the answer to the question of "the next step for domestic chips" on the table so concretely for the first time.
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