软件:Quartus
语言:VHDL
代码功能:
按键加减计数器
1、设计加减计数器,通过按键控制加减
2、分别有加按键和减按键,按下加一或者减1
3、数码管显示当前计数值
FPGA代码Verilog/VHDL代码资源下载:www.hdlcode.com
演示视频:
设计文档:
Testbench
部分代码展示:
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY key_jishu IS PORT ( rst : IN STD_LOGIC;--低电平有效 key_in : IN STD_LOGIC;--低电平有效 key_sub : IN STD_LOGIC;--低电平有效--减法 clk : IN STD_LOGIC;--clk1_50M duanxuan : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);--高电平有效 weixuan : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--低电平有效 ); END key_jishu; ARCHITECTURE trans OF key_jishu IS SIGNAL display : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11000000"; SIGNAL dis_num_gewei : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; SIGNAL dis_num_shiwei : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000"; SIGNAL key_out : STD_LOGIC := '1';--加法 SIGNAL key_out_sub : STD_LOGIC := '1';--减法 SIGNAL key_en : STD_LOGIC := '0'; SIGNAL cnt : STD_LOGIC_VECTOR(31 DOWNTO 0) := "00000000000000000000000000000000"; SIGNAL select_num : STD_LOGIC_VECTOR(31 DOWNTO 0) := "00000000000000000000000000000000"; SIGNAL geshu : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000"; SIGNAL sample_en : STD_LOGIC := '0'; BEGIN --////////////////////////////////////////////位选//////////////////////////////////////////////// PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (select_num = "00000000000000011000011010011111") THEN select_num <= "00000000000000000000000000000000";--扫描频率 ELSE select_num <= select_num + "00000000000000000000000000000001";--扫描频率计时数字 END IF; END IF; END PROCESS; PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (select_num = "00000000000000011000011010011111") THEN IF (geshu = "001") THEN geshu <= "000"; ELSE geshu <= geshu + "001";--扫描哪个管子的指示位 END IF; END IF; END IF; END PROCESS; PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN CASE geshu IS--位选切换 WHEN "000" => weixuan <= "01"; display <= dis_num_gewei; WHEN "001" => weixuan <= "10"; display <= dis_num_shiwei; WHEN OTHERS => END CASE; END IF; END PROCESS; --////////////////////////////////////////////按键加1模块,减1模块////////////////////////////////////////////// PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (rst = '0') THEN dis_num_gewei <= "00000000"; dis_num_shiwei <= "00000000"; END IF; --加法 IF (key_out = '0' AND rst = '1') THEN IF (dis_num_gewei = "00001001") THEN--个位=9 IF (dis_num_shiwei = "00001001") THEN--十位==9 dis_num_gewei <= "00000000"; dis_num_shiwei <= "00000000"; ELSE dis_num_shiwei <= dis_num_shiwei + "00000001";--十位 dis_num_gewei <= "00000000"; END IF; ELSE dis_num_gewei <= dis_num_gewei + "00000001";--个位 dis_num_shiwei <= dis_num_shiwei; END IF; --减法 ELSIF (key_out_sub= '0' AND rst = '1') then IF (dis_num_gewei = "00000000") THEN--个位=0 IF (dis_num_shiwei = "00000000") THEN--十位==0 dis_num_gewei <= "00001001"; dis_num_shiwei <= "00001001"; ELSE dis_num_shiwei <= dis_num_shiwei - "00000001";--十位 dis_num_gewei <= "00001001";--十位==9 END IF; ELSE dis_num_gewei <= dis_num_gewei - "00000001";--个位 dis_num_shiwei <= dis_num_shiwei; END IF; END IF; END IF; END PROCESS; --////////////////////////////////////////////按键消抖模块////////////////////////////////////////////// PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (rst = '0') THEN cnt <= "00000000000000000000000000000000"; ELSE IF (cnt = "00000000000000000000000001111111") THEN--计时200mS cnt <= "00000000000000000000000000000000"; ELSE cnt <= cnt + "00000000000000000000000000000001"; END IF; END IF; END IF; END PROCESS; PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (rst = '0') THEN sample_en <= '0'; ELSE IF (cnt = "00000000000000000000000001111111") THEN--计时200mS sample_en <= '1'; ELSE sample_en <= '0'; END IF; END IF; END IF; END PROCESS; PROCESS (clk) BEGIN IF (clk'EVENT AND clk = '1') THEN IF (rst = '0') THEN key_out <= '1'; key_out_sub<='1'; ELSE IF (sample_en = '1') THEN--消抖后采样频率 key_out <= key_in;--采样按键是否按下 key_out_sub<=key_sub;--采样按键是否按下 ELSE key_out <= '1'; key_out_sub<='1'; END IF; END IF; END IF; END PROCESS;
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