基于FPGA的数字钟设计Verilog代码VIVADO仿真

名称：基于FPGA的数字钟设计Verilog代码VIVADO仿真

软件：VIVADO

语言：Verilog

代码功能：数字钟设计

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

仿真

clk_div模块

Testbench

仿真图

x8seg模块

Testbench

仿真图

binbcd8模块

Testbench

仿真图

clock_ctrl模块

Testbench

仿真图

部分代码展示:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/14 14:32:03
// Design Name: 
// Module Name: clock_top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
module clock_top(
input clk_100MHz,
input clr,
input en,
input mode,
input inc,
output[7:0] a_to_h_0,
output[7:0] a_to_h_1,
output[7:0]an
    );
    wire clk_200Hz;
    wire clk_10Hz;
    wire clk_1Hz;
    wire [7:0]hour;
    wire [7:0]min;
    wire[7:0] sec;
    wire incd;
    wire moded;
    wire [7:0]a_to_g_hour;
    wire [7:0]a_to_g_min;
    wire [7:0]a_to_g_sec;
    wire[2:0] blink;
    wire [3:0] dp;
    clk_div U1(.clk_100MHz(clk_100MHz),
               .clk_200Hz(clk_200Hz),
               .clk_10Hz(clk_10Hz),
               .clk_1Hz(clk_1Hz)
     );
     debounce U2(.clk_200Hz(clk_200Hz),
                 .clr(~clr),
                 .inp({inc,mode}),
                 .outp({incd,moded})
     );
     clocks_ctrl U3(.clk_1Hz(clk_1Hz),
                     .clk_10Hz(clk_10Hz),
                     .clr(~clr),
                     .en(en),
                     .mode(moded),
                     .inc(incd), 
                     .hour(hour),
                     .min(min),
                     .sec(sec),
                     .blink(blink)
      );
      binbcd8 U4(.b(hour),
                 .p(a_to_g_hour)
      );          
      binbcd8 U5(.b(min),
                 .p(a_to_g_min)
      );          
      binbcd8 U6(.b(sec),
                 .p(a_to_g_sec)
            );  
      x8seg U7(.clk(clk_200Hz),
               .x({a_to_g_min,a_to_g_sec}),
               .blink(blink[1:0]),
               .dp(4'b0100),
               .a_to_h(a_to_h_0),
               .an(an[3:0])
      );
      x8seg U8(.clk(clk_200Hz),
                    .x({8'b0,a_to_g_hour}),
                    .blink({1'b0,blink[2]}),
                    .dp(4'b0001),
                    .a_to_h(a_to_h_1),
                    .an(an[7:4])
      );
                       
endmodule

点击链接获取代码文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=861