数模转换AD5545芯片驱动程序设计Verilog代码VIVADO仿真

名称：数模转换AD5545芯片驱动程序设计Verilog代码VIVADO仿真

软件：VIVADO

语言：Verilog

代码功能：数模转换AD5545芯片驱动程序

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

演示视频：

设计文档：

1. 工程文件

2. 程序文件

3. 程序编译

4. Testbench

5. 仿真图

部分代码展示:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/10/10 22:06:23
// Design Name: 
// Module Name: AD5545_drive
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
//数据速率为1M，AB分别0.5M
module AD5545_drive(
    input clk_200M,
    input [15:0] data_A,
    input [15:0] data_B,
    output reg DA_SDI,
    output reg DA_CLK,
    output reg DA_CS_n,
    output reg DA_LDAC_n
    );
reg flag_AB=0;
reg [1:0] A1A0=2'd0;//01--A;10--B
reg [15:0] data_DA=16'd0;//DA数据
reg [7:0] count=8'd0;//计数器
always@(posedge clk_200M)
    if(count==8'd199)
        flag_AB<=~flag_AB;//flag_AB==0时输出A数据，=1时输出B数据
always@(posedge clk_200M)
    if(flag_AB==0)begin//flag_AB==0时输出A数据，=1时输出B数据
        A1A0<=2'b01;//01--A;10--B
        data_DA<=data_A;
        end
     else begin
        A1A0<=2'b10;//01--A;10--B
        data_DA=8'd199)
        count<=8'd0;
    else
        count<=count+8'd1;
//count=0~5---cs=1 ldac=1;
//count=6~150---cs=0 ldac=1;
//count=160~200---cs=1 ldac=0;
//控制DA_CS_n
always@(posedge clk_200M)
    if(count<8'd6)
        DA_CS_n8'd159)
        DA_CS_n<=1;
    else
        DA_CS_n<=0;
//控制DA_LDAC_n
always@(posedge clk_200M)
    if(count8'd170)
        DA_LDAC_n<=0;
    else
        DA_LDAC_n<=1;
//控制DA_CLK
always@(posedge clk_200M)
    case(count)
        8'd10:DA_CLK<=1;//第1个时钟
        8'd14:DA_CLK<=0;
        
        8'd18:DA_CLK<=1;//第2个时钟
        8'd22:DA_CLK<=0;
        
        8'd26:DA_CLK<=1;//第3个时钟
        8'd30:DA_CLK<=0;
        
        8'd34:DA_CLK<=1;//第4个时钟
        8'd38:DA_CLK<=0;
        
        8'd42:DA_CLK<=1;//第5个时钟
        8'd46:DA_CLK<=0;
        8'd50:DA_CLK<=1;//第6个时钟
        8'd54:DA_CLK<=0;
        8'd58:DA_CLK<=1;//第7个时钟
        8'd62:DA_CLK<=0;
        8'd66:DA_CLK<=1;//第8个时钟
        8'd70:DA_CLK<=0;
        8'd74:DA_CLK<=1;//第9个时钟
        8'd78:DA_CLK<=0;
        8'd82:DA_CLK<=1;//第10个时钟
        8'd86:DA_CLK<=0;
        8'd90:DA_CLK<=1;//第11个时钟
        8'd94:DA_CLK<=0;
        8'd98:DA_CLK<=1;//第12个时钟
        8'd102:DA_CLK<=0;
        8'd106:DA_CLK<=1;//第13个时钟
        8'd110:DA_CLK<=0;
        8'd114:DA_CLK<=1;//第14个时钟
        8'd118:DA_CLK<=0;
        8'd122:DA_CLK<=1;//第15个时钟
        8'd126:DA_CLK<=0;
        8'd130:DA_CLK<=1;//第16个时钟
        8'd134:DA_CLK<=0;
        8'd138:DA_CLK<=1;//第17个时钟
        8'd142:DA_CLK<=0;
        8'd146:DA_CLK<=1;//第18个时钟
        8'd150:DA_CLK<=0;

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