名称:MiniZed开发板实现串口发送和接收(代码在文末付费下载)
软件:VIVADO
语言:Verilog
顶层代码
module uart_test(
input clk,
input rst_n,
input uart_rx,
input[7:0] tx_data,
output[7:0] rx_data,
output uart_tx
);
parameter CLK_FRE = 50;//Mhz
wire tx_data_valid;
wire tx_data_ready;
wire rx_data_valid;
wire rx_data_ready;
assign rx_data_ready = 1'b1;//always can receive data
assign tx_data_valid = 1'b1;
uart_rx#
(
.CLK_FRE(CLK_FRE),
.BAUD_RATE(9600)
) uart_rx_inst
(
.clk (clk ),
.rst_n (rst_n ),
.rx_data (rx_data ),
.rx_data_valid (rx_data_valid ),
.rx_data_ready (rx_data_ready ),
.rx_pin (uart_rx )
);
uart_tx#
(
.CLK_FRE(CLK_FRE),
.BAUD_RATE(9600)
) uart_tx_inst
(
.clk (clk ),
.rst_n (rst_n ),
.tx_data (tx_data ),
.tx_data_valid (tx_data_valid ),
.tx_data_ready (tx_data_ready ),
.tx_pin (uart_tx )
);
endmodule
开发板资料:
constraint.docx
[PRJ-MI1DEV,1-01-04]_Schematic Prints.pdf
MiniZed-HW-UG-v1-0-V1_0.pdf
代码文件:
点击链接获取代码文件:http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=135
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