芯耀
85
名称
软件
Quartus II
语言
VHDL
代码功能
本设计实现了一个基于FPGA的8位直接测频频率计，能够对输入信号进行频率测量，并通过数码管实时显示测量结果。系统采用1秒门控方式，统计输入信号在门控时间内的周期数，最终将频率值锁存并显示。适用于需要高精度频率测量的场合。
演示视频：
代码实现思路
系统由多个功能模块组成：
·控制模块（Frq_Ctrl）产生门控信号、复位信号和锁存信号，实现测量周期的控制。
·计数器模块（counter）在门控信号有效期间统计输入信号的周期数，输出频率值。
·锁存模块（data_store）在锁存信号到来时，将计数器输出的频率值锁存。
·显示模块（LED_DISP）将锁存的频率值转换为数码管显示格式，驱动8位数码管显示。 各模块通过信号线连接，协同完成频率测量和显示。整体设计结构清晰，易于扩展和维护。
代码结构
·Freq_test：顶层模块，连接各功能模块，实现系统集成。
·Frq_Ctrl：控制模块，负责门控、复位和锁存信号的生成。
·counter：计数器模块，统计输入信号周期数，输出频率值。
·data_store：锁存模块，保存测量到的频率值。
·LED_DISP：显示模块，将频率值转换为数码管显示格式。
1、工程文件
2、程序文件
3、程序编译
4、RTL图
5、testbench
6、仿真图
整体仿真图
控制模块
计数器模块
锁存器模块
数码管显示模块
部分代码展示
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; --计数器模块 ENTITY counter IS PORT ( signal_in : IN STD_LOGIC;--被测信号 en : IN STD_LOGIC;--1S闸门信号 rst : IN STD_LOGIC; number : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)--频率值 ); END counter; ARCHITECTURE behavioral OF counter IS SIGNAL num_0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; SIGNAL num_1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; SIGNAL num_2 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; SIGNAL num_3 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; SIGNAL num_4 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; SIGNAL num_5 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; SIGNAL num_6 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; SIGNAL num_7 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; BEGIN number <= (num_7 & num_6 & num_5 & num_4 & num_3 & num_2 & num_1 & num_0);--单位Hz --计数,计数1s内的信号周期数，计数值就是频率值 PROCESS (signal_in, rst) BEGIN IF (rst = '1') THEN num_0 <= "0000"; num_1 <= "0000"; num_2 <= "0000"; num_3 <= "0000"; num_4 <= "0000"; num_5 <= "0000"; num_6 <= "0000"; num_7 <= "0000"; ELSIF (signal_in'EVENT AND signal_in = '1') THEN IF (en = '1') THEN--计数，低位都是9，则高位加1，低位清零，例如加到9999，则变为10000 IF (num_6 = "1001" AND num_5 = "1001" AND num_4 = "1001" AND num_3 = "1001" AND num_2 = "1001" AND num_1 = "1001" AND num_0 = "1001") THEN num_0 <= "0000"; num_1 <= "0000"; num_2 <= "0000"; num_3 <= "0000"; num_4 <= "0000"; num_5 <= "0000"; num_6 <= "0000"; num_7 <= num_7 + "0001";--低位为9，则高位加1，低位清零 ELSIF (num_5 = "1001" AND num_4 = "1001" AND num_3 = "1001" AND num_2 = "1001" AND num_1 = "1001" AND num_0 = "1001") THEN num_0 <= "0000"; num_1 <= "0000"; num_2 <= "0000"; num_3 <= "0000"; num_4 <= "0000"; num_5 <= "0000"; num_6 <= num_6 + "0001";--低位为9，则高位加1，低位清零 num_7 <= num_7; ELSIF (num_4 = "1001" AND num_3 = "1001" AND num_2 = "1001" AND num_1 = "1001" AND num_0 = "1001") THEN num_0 <= "0000"; num_1 <= "0000"; num_2 <= "0000"; num_3 <= "0000"; num_4 <= "0000"; num_5 <= num_5 + "0001";--低位为9，则高位加1，低位清零 num_6 <= num_6; num_7 <= num_7; ELSIF (num_3 = "1001" AND num_2 = "1001" AND num_1 = "1001" AND num_0 = "1001") THEN num_0 <= "0000"; num_1 <= "0000"; num_2 <= "0000"; num_3 <= "0000"; num_4 <= num_4 + "0001";--低位为9，则高位加1，低位清零 num_5 <= num_5; num_6 <= num_6; num_7 <= num_7; ELSIF (num_2 = "1001" AND num_1 = "1001" AND num_0 = "1001") THEN num_0 <= "0000"; num_1 <= "0000"; num_2 <= "0000"; num_3 <= num_3 + "0001";--低位为9，则高位加1，低位清零 num_4 <= num_4; num_5 <= num_5; num_6 <= num_6; num_7 <= num_7; ELSIF (num_1 = "1001" AND num_0 = "1001") THEN num_0 <= "0000"; num_1 <= "0000"; num_2 <= num_2 + "0001";--低位为9，则高位加1，低位清零 num_3 <= num_3; num_4 <= num_4; num_5 <= num_5; num_6 <= num_6; num_7 <= num_7; ELSIF (num_0 = "1001") THEN num_0 <= "0000"; num_1 <= num_1 + "0001";--低位为9，则高位加1，低位清零 num_2 <= num_2; num_3 <= num_3; num_4 <= num_4; num_5 <= num_5; num_6 <= num_6; num_7 <= num_7; ELSE num_0 <= num_0 + "0001";--低位加1 num_1 <= num_1; num_2 <= num_2; num_3 <= num_3; num_4 <= num_4; num_5 <= num_5; num_6 <= num_6; num_7 <= num_7; END IF; END IF; END IF; END PROCESS; END behavioral;
代码获取（付费后可见）：
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